- sample-micro-arch, [1], [2], [3]
- sample_micro_arch, [1]
- sc, [1]
- scs, [1]
- self-consistency, [1]
- SIM_break_cycle(cpu, 0), [1]
- SIM_break_simulation, [1]
- SIM_instruction_begin, [1], [2], [3]
- SIM_instruction_child, [1]
- SIM_instruction_commit, [1], [2], [3], [4]
- SIM_instruction_cpu, [1]
- SIM_instruction_decode, [1], [2], [3]
- SIM_instruction_end, [1], [2], [3]
- SIM_instruction_execute, [1], [2], [3]
- SIM_instruction_fetch, [1], [2]
- SIM_instruction_force_correct, [1], [2]
- SIM_instruction_get_field_value, [1]
- SIM_instruction_get_reg_info, [1], [2]
- SIM_instruction_get_user_data, [1]
- SIM_instruction_handle_exception, [1], [2], [3], [4]
- SIM_instruction_handle_interrupt, [1], [2], [3], [4]
- SIM_instruction_id_from_mem_op_id, [1]
- SIM_instruction_insert, [1], [2], [3]
- SIM_instruction_is_sync, [1], [2]
- SIM_instruction_length, [1]
- SIM_instruction_nth_id, [1]
- SIM_instruction_opcode, [1], [2]
- SIM_instruction_parent, [1]
- SIM_instruction_phase, [1]
- SIM_instruction_proceed, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11]
- SIM_instruction_read_input_reg, [1], [2]
- SIM_instruction_read_output_reg, [1]
- SIM_instruction_remaining_stall_time, [1], [2], [3]
- SIM_instruction_retire, [1], [2]
- SIM_instruction_rewind, [1]
- SIM_instruction_set_right_path, [1]
- SIM_instruction_set_stop_phase, [1], [2]
- SIM_instruction_set_user_data, [1]
- SIM_instruction_speculative, [1]
- SIM_instruction_squash, [1], [2]
|
- SIM_instruction_stalling_mem_op, [1]
- SIM_instruction_status, [1]
- SIM_instruction_store_queue_mem_op, [1]
- SIM_instruction_type, [1], [2]
- SIM_instruction_write_input_reg, [1], [2], [3], [4]
- SIM_instruction_write_output_reg, [1]
- SIM_instruction_wrong_path, [1]
- SMP, [1]
- SMT, [1]
- speculation
-
control, [1]
-
data, [1]
- speculation points, [1]
- speculative
-
path, [1]
- squash, [1]
- squashing
instructions, [1]
- stalling (status), [1]
- status
-
faulting, [1]
-
interrupt, [1]
-
ready, [1]
-
stalling, [1]
-
trap, [1]
-
waiting, [1]
- STC, [1]
- step-break, [1]
- step-break-absolute, [1]
- step-cycle, [1], [2]
- step-cycle-single, [1]
- step-instruction, [1]
- store
queue, [1]
- store transaction, [1]
- store-load consistency, [1]
- store-store consistency, [1]
- swap
instructions, [1]
- synchronous instructions, [1]
- synchronous registers, [1]
|