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Index

Symbols

[simics], [1]
[workspace], [1]

A

address calculation phase, [1]
anti-dependencies, [1]
architectural state, [1], [2]
architectural state, [1], [2], [3], [4], [5], [6]
Asynchronous_Trap, [1]
atomic instructions, [1]
atomic instructions, [1]
atomic operations, [1], [2]
auto_speculate_cwp, [1]

B

block operation, [1], [2]
branch speculation, [1]
Branch Target Buffer, [1]
breakpoints, [1]
BTB, [1]

C

checkpoint, [1]
checkpointing, [1]
commit phase, [1]
commit phase, [1]
commits_per_cycles, [1], [2]
config_accept_no_stall, [1]
config_max_out_trans, [1]
config_read_per_cycle, [1]
config_write_per_cycle, [1]
consistency controller, [1]
consistency controller, [1], [2]
continue, [1]
control dependence, [1]
control speculation, [1]
control transactions, [1]
correct instruction, [1]
CWP, [1]
cycle handler, [1]
cycle handler, [1], [2], [3]

D

data speculation, [1]
data-dependencies, [1]
decode phase, [1], [2]
dependences, [1]
dependencies
anti, [1]
control, [1]
data, [1]
memory, [1]
name, [1]
RAW, [1]
register, [1]
WAR, [1]
WAW, [1]
discarding instructions, [1]

E

execute phase, [1]
execute phase, [1]
execute_per_cycles, [1], [2]

F

faulting (status), [1]
faulting instruction, [1]
fetch phase, [1], [2]
fetches_per_cycles, [1], [2]

G

g-cache, [1], [2]
g-cache-ooo, [1], [2]
global commit phase, [1]

I

incorrect instruction, [1]
input values, [1]
instruction
correct, [1]
discarding, [1]
id, [1]
incorrect, [1]
phases, [1]
speculative, [1], [2]
squashing, [1]
instruction fetches, [1], [2]
instruction tree, [1]
instruction-fetch-mode, [1]
instruction-fetch-trace, [1]
instruction_error_t, [1]
instructions
synchronous, [1]
interrupt vector, [1]
interrupt (status), [1]
interrupts, [1]

L

load-load consistency, [1]
load-store consistency, [1]
load-store queue, [1]
locking ram, [1]
locking granularity, [1]
locking transactions, [1]
LSQ, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10]
atomic instructions, [1]
device loads, [1]
device stores, [1]
loads, [1]
stores, [1]

M

magic breakpoints, [1]
memory consistency, [1]
memory dependencies, [1]
MESI, [1]
multi-processors, [1]
multiple outstanding transactions, [1]

N

name-dependencies, [1]
nPC, [1]

O

ooo-micro-arch, [1], [2], [3]
ooo_micro_arch, [1]
out-of-order
retire, [1]
out-of-order window, [1]
out_of_order_retire, [1]
output values, [1]

P

page_cross, [1]
Parameterized Mode, [1]
phase, [1]
commit, [1], [2]
decode, [1], [2]
execute, [1], [2]
fetch, [1], [2]
init, [1]
retire, [1], [2]
piq, [1]
prefetch transactions, [1]
prefetching (see explanations below), [1]
print-instruction-queue, [1], [2], [3]
program counter, [1]
program order consistency, [1]

R

RAW, [1]
read-after-write, [1]
ready (status), [1]
reg_info_t, [1]
register renaming, [1]
register-pool, [1]
reorder_buffer_size, [1]
retire phase, [1], [2]
retires_per_cycles, [1]
run, [1], [2]
run-cycles, [1]

S

sample-micro-arch, [1], [2], [3]
sample_micro_arch, [1]
sc, [1]
scs, [1]
self-consistency, [1]
SIM_break_cycle(cpu, 0), [1]
SIM_break_simulation, [1]
SIM_instruction_begin, [1], [2], [3]
SIM_instruction_child, [1]
SIM_instruction_commit, [1], [2], [3], [4]
SIM_instruction_cpu, [1]
SIM_instruction_decode, [1], [2], [3]
SIM_instruction_end, [1], [2], [3]
SIM_instruction_execute, [1], [2], [3]
SIM_instruction_fetch, [1], [2]
SIM_instruction_force_correct, [1], [2]
SIM_instruction_get_field_value, [1]
SIM_instruction_get_reg_info, [1], [2]
SIM_instruction_get_user_data, [1]
SIM_instruction_handle_exception, [1], [2], [3], [4]
SIM_instruction_handle_interrupt, [1], [2], [3], [4]
SIM_instruction_id_from_mem_op_id, [1]
SIM_instruction_insert, [1], [2], [3]
SIM_instruction_is_sync, [1], [2]
SIM_instruction_length, [1]
SIM_instruction_nth_id, [1]
SIM_instruction_opcode, [1], [2]
SIM_instruction_parent, [1]
SIM_instruction_phase, [1]
SIM_instruction_proceed, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11]
SIM_instruction_read_input_reg, [1], [2]
SIM_instruction_read_output_reg, [1]
SIM_instruction_remaining_stall_time, [1], [2], [3]
SIM_instruction_retire, [1], [2]
SIM_instruction_rewind, [1]
SIM_instruction_set_right_path, [1]
SIM_instruction_set_stop_phase, [1], [2]
SIM_instruction_set_user_data, [1]
SIM_instruction_speculative, [1]
SIM_instruction_squash, [1], [2]
SIM_instruction_stalling_mem_op, [1]
SIM_instruction_status, [1]
SIM_instruction_store_queue_mem_op, [1]
SIM_instruction_type, [1], [2]
SIM_instruction_write_input_reg, [1], [2], [3], [4]
SIM_instruction_write_output_reg, [1]
SIM_instruction_wrong_path, [1]
SMP, [1]
SMT, [1]
speculation
control, [1]
data, [1]
speculation points, [1]
speculative
path, [1]
squash, [1]
squashing instructions, [1]
stalling (status), [1]
status
faulting, [1]
interrupt, [1]
ready, [1]
stalling, [1]
trap, [1]
waiting, [1]
STC, [1]
step-break, [1]
step-break-absolute, [1]
step-cycle, [1], [2]
step-cycle-single, [1]
step-instruction, [1]
store queue, [1]
store transaction, [1]
store-load consistency, [1]
store-store consistency, [1]
swap instructions, [1]
synchronous instructions, [1]
synchronous registers, [1]

T

trap (status), [1]

V

value prediction, [1]

W

waiting (status>), [1]
WAR, [1]
WAW, [1]
write-after-read, [1]
write-after-write, [1]

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