Synchronized instructions of type 1:
ENTER | allocate stack space when entering procedure |
POPA(D) | pop all registers from stack |
PUSHA(D) | push all registers onto the stack |
Synchronized instructions of type 2:
CALL | call procedure (in other seg.) |
CLFLUSH | Flushes cache lines |
CLI | clear interrupt flag |
CLTS | clear task-switched flag in CR0 |
CPUID | returns processor identification information |
EMMS | empty MMX state |
FP instr. | |
FXRSTOR | restore x87 FPU, MMX, XMM, and MXCSR state |
HLT | halt |
IN | input from port; fixed port |
IN | nput from port; variable port |
(REP) INS | input from DX port |
INT1 | |
INT n | interrupt type n |
INTO | interrupt 4 on overflow |
INT | single step interrupt 3 |
INVD | invalidate cache |
INVLPG | Invalidate TLB Entry |
IRET/IRETD | interrupt return |
JMP | unconditional jump (to other seg.) |
JMP | unconditional jump (to other seg.) |
LDMXCSR | Load MXCSR |
LDS | load pointer to DS |
LES | load pointer to ES |
LFENCE | Serializes load operations |
LFS | load pointer to FS |
LGDT | Load Global Descriptor Table Register |
LGS | load pointer to GS |
LLDT | Load Local Descriptor Table Register |
LMSW | Load Machine Status Word |
LOCK prefixed instr. | |
LSS | load pointer to SS |
LTR | Load Task Register |
MFENCE | Serializes load and store operations |
MOV | data to segment register |
MOV | move to control register |
MOV | move to debug register |
OUT | output to port; fixed port |
OUT | output to port; variable port |
OUTS | output to DX port |
POP | pop top of stack into DS |
POP | pop top of stack into FS |
POP | pop top of stack into GS |
PUSH | push CS onto the stack |
PUSH | push DS word onto the stack |
PUSH | push ES onto stack |
PUSH | push SS onto stack |
RET | return from procedure (to other seg) |
RSM | resume from system management mode |
SFENCE | Serializes store operations |
STI | set interrupt flag |
SYSENTER | fast call to pl 0 system procedures |
SYSEXIT | fast return from fast system call |
WAIT | wait |
WBINVD | write-back and invalidate data cache |
WRMSR | write to model-specific register |