CS 885 : Future Multicore Architectures and their Software

Summer 2012
Instructor Arrvindh Shriraman
Office : 4172 Surrey Campus, 9213 Burnaby Campus
Email :
Office hours : Fri (3-4:30 starting May 20th). Feel free to stop by and check.

What is the class about?

Ever wondered about how powerful your iphone is ? Is it a capable desktop replacement ? Ever thought what google looks like inside ? First step to a successful software product is knowing your target hardware ? There is no iphone OS without the Apple A4 processor or google.com without the massive datacenter?

Are you interested in understanding the architecture of cutting-edge systems that you will be programming in the future and what challenges confront software?

This course is designed to cover emeging trends in computer architecture (e.g., multicore processors, GPUs, cellphone-class hardware) and analyze the major challenges (e.g., parallelism) that confront software developers and what software needs to do to overcome these challenges.

In the first half we will focus on the trend of Parallelism . We will begin with a primer on multicore manycore chips: chips that integrate multiple CPUs on the same. Intel is shipping 10 core (20 thread chips) and our own AMD servers are 2 chip 24-thread systems. All new chips build today and in the future will be multicore chips. They are ubiquitous and are present in your laptops, cell phones, and gaming consoles. Cell phone processor designs are more aggressive and include a collection of heterogeneous cores like signal processors and crypographic units along with a traditional processor. Harnessing these new age compute engines is an open challenge. We will focus on their architectures different programming models that empower us to tap into this fountain of CPUs.

In the second half we will focus on Energy-Efficiency . We will discuss why modern multicore chips are woefully in-effficient and waste a lot of energy in doing extraneous work. With each technology generation you get more transistors, but the percent of a chip you can actively use drops exponentially --- in 2020 we can only operate 4% of the chip. We will look at the emergence of energy-efficient memory technologies and chips like GPUs and Cell phone chips which laugh at the face of the power wall. Modern chips also present a number of dynamic power knobs that can be tuned to change the energy profile of a processor. We will discuss the role of software in aiding hardware achieve energy-efficient execution. We will look at programming models and execution patterns that lead to energy-efficient computing. We will study how in certain applications we can trade off quality-of-service guarantees for energy gains and learn how to build in the QOS hints into software. Finally, we will elaborate on adaptive software runtimes that tune the various power knobs in existing systems.