Interrupt a Sparc Processor.
This interface is implemented by sparc processors to be able to receive interrupts or asynchronous traps. The arguments to the interrupt_cpu the cpu to interrupt (cpu), a pointer to the sending object (obj), the mid of the sending object (source_mid), the mid of the target object (target_mid), and a callback function that will be called when it is determined if the CPU can receive the interrupt (irq_ack_cb). There is also a data pointer (data), pointing to an array of 64-bit integers, and a user pointer (callback_data) that is returned by the ack callback to the caller. In the callback, the result is returned as the argument ack, which is either 0 for ACK or 1 for NACK.
The trap_cpu function can be used for disrupting and deferred traps. The trap will be inserted after the current executing instruction. If Simics is run in out of order execution mode, the trap will occur when all instructions in the reorder buffer have completed.
Precise traps can be injected by instructions accessing memory. This is done by setting the exception field of a generic_transaction_t in the operate function of a timing model interface. It is thus necessary to create a timing model object to be able to inject precise traps.
typedef void (*interrupt_ack_t)(conf_object_t *obj,
conf_object_t *cpu,
int cpu_mid,
int ack,
lang_void *usr);
typedef void (*interrupt_cpu_t)(conf_object_t *cpu,
conf_object_t *obj,
int source_mid,
int target_mid,
interrupt_ack_t irq_ack_cb,
uint64 *data,
lang_void *usr,
int dummy1, int dummy2);
typedef void (*trap_cpu_t)(conf_object_t *cpu,
exception_type_t trap_vector);
typedef struct sparc_interrupt_interface {
interrupt_cpu_t interrupt_cpu;
trap_cpu_t trap_cpu;
} sparc_interrupt_interface_t;
#define SPARC_INTERRUPT_INTERFACE "sparc-interrupt"