ultrasparc-iii-plus

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ultrasparc-iii-plus

Provided by: sparc-u3, sparc-u3-ma, sparc-u3-turbo
Class Hierarchy: conf-object → log-object → ultrasparc-iii-plus
Interfaces Implemented: log_object, sparc_u3, sparc_v9, sparc_interrupt, exception, int_register, processor, event_poster
Description: The ultrasparc-iii-plus class implements an UltraSPARC III Cu (III+) processor.

Attributes

Attributes inherited from class conf-object

attributes, classname, component, iface, name, object_id, queue

Attributes inherited from class log-object

access_count, log_buffer, log_buffer_last, log_buffer_size, log_group_mask, log_groups, log_level, log_type_mask

Attribute List

address_width: Pseudo class attribute; read-only access; type: unknown type.
(phys-bits, virt-bits) Number of bits in physical and virtual addresses.

afar_priority: Optional attribute; read/write access; type: [ii].
(priority, bit) The number of the owning AFSR bit of the AFAR register, and its priority level.

afsr_e_synd_priority: Optional attribute; read/write access; type: [ii].
(priority, bit) The number of the owning AFSR bit of the AFSR.E_SYND register, and its priority level.

afsr_m_synd_priority: Optional attribute; read/write access; type: [ii].
(priority, bit) The number of the owning AFSR bit of the AFSR.M_SYND register field, and its priority level.

aprof_views

Session attribute; read/write access; type: [[o,i]*].

((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.

This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.

architecture: Pseudo class attribute; read-only access; type: unknown type.
Implemented architecture (sparc-v9)

asi_names: Pseudo attribute; read-only access; type: [s*]; integer indexed; indexed type: i|[ii].
List of all ASI names

auto_speculate_cwp: Optional attribute; read/write access; type: b.
If set to TRUE, Simics will speculate on the value of the CWP register by inspecting save, restore, and return instructions in MAI mode.

big_endian: Pseudo attribute; read-only access; type: b.
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.

branch_prof_support: Pseudo attribute; read-only access; type: b.
True if this processor supports branch profiling in -stall mode, false otherwise.

branch_recorders: Session attribute; read/write access; type: [o*].
Branch recorders attached to this processor.

break_on_error_state: Session class attribute; read/write access; type: b.
Break the simulation if a processor enters error_state

committed_instructions: Pseudo attribute; read-only access; type: Integer.
Number of committed instructions for an out of order target.Same as step count for an in-order Simics.

control_registers: Optional attribute; read/write access; type: [[si]*]; integer or string indexed; indexed type: Integer.
List of all control registers. The attribute supports both integer and string indexed.

cpu_group: Required attribute; read/write access; type: Object.
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface and the sparc-irq-businterface.

current_context: Session attribute; read/write access; type: Object.
Current context object.

current_globals: Pseudo attribute; read-only access; type: Integer.
Number of the current set of global registers.

cycle_fractions: Optional attribute; read/write access; type: Integer.
Modeling parameter related to processor scheduling.

cycles: Optional attribute; read/write access; type: Integer.
Time measured in cycles from machine start.

dbg_compile_block: Pseudo attribute; write-only access; type: unknown type.
Force compile of block.

do_allocate_target_registers: Session class attribute; read/write access; type: unknown type.
Target register allocation enable.

do_reissue: Session attribute; write-only access; type: Integer.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.

enabled_flag: Optional attribute; read/write access; type: b.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.

event_desc: Pseudo attribute; read-only access; ; integer indexed; indexed type: [[o|n,s,i]*].
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).

extra_irq_enable: Pseudo attribute; read/write access; type: b.
The value if this attribute is used as a second interrupt enable flag for the processor. For interrupts to be enabled, the pstate.ie must be 1 and extra_irq_enable must be set to .TRUE. The default value is TRUE.

fp_registers: Optional attribute; read/write access; type: [i{32}].
List of all floating point registers.

freq_mhz: Required attribute; read/write access; type: i|f.
Processor clock frequency in MHz.

global_registers: Optional attribute; read/write access; type: [[i{8}]{4}].
List of all global registers.

global_set_names: Pseudo attribute; read-only access; type: [ssss].
Names of the four sets with global registers.

impl_dep_125_no_clear: Optional attribute; read/write access; type: b.
If TRUE, the upper 32 bits of PC will not be cleared (even if pstate.am is 1) on register writes caused by 'call' 'jmpl', 'rdpc' and traps.

instruction_fetch_line_size: Session attribute; read/write access; type: Integer.
Instruction fetch line size for this processor.

instruction_fetch_mode: Session attribute; read/write access; type: String.
Instruction fetch mode

is_stalling: Optional attribute; read/write access; type: b.
TRUE if the processor is currently stalling by request of a timing-model.

lock_granularity: Optional attribute; read/write access; type: Integer.
Lock granularity of atomic instructions

lsq_enabled: Optional attribute; read/write access; type: Integer.
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"

mai_debug: Optional attribute; read/write access; type: String.
(internal) Set debug file for MAI

max_trap_levels: Optional attribute; read/write access; type: Integer.
The number of trap levels.

memory_profilers: Session attribute; read/write access; type: [o|n*]; integer indexed; indexed type: Object or Nil.
Memory read/write profilers.

memory_profiling_granularity_log2: Pseudo attribute; read-only access; type: Integer.
Base 2 logarithm of memory profiling granularity.

min_cacheline_size: Pseudo attribute; read-only access; type: Integer.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).

mmu: Required attribute; read/write access; type: Object.
The associated MMU object, implementing the 'mmu' interface.

mode_counters: Pseudo attribute; read-only access; type: [[sii]*].
((name, user-value, supervisor-value), ...) List of per-mode counters.

no_unpriv_nucleus_ifetch: Optional attribute; read/write access; type: b.
If set, unprivileged instruction fetches are not allowed from nucleus ASI.

num_windows: Optional attribute; read/write access; type: Integer.
Number of register windows.

ooo_mode: Optional attribute; read/write access; type: String.
"in-order" or "micro-architecture".

pending_exception: Optional attribute; read/write access; type: Integer.
The exception number of any pending exception.

pending_interrupt: Optional attribute; read/write access; type: Integer.
Set to 0x60 (Interrupt_Vector) if an external interrupt is pending. 1 - 15 for soft interrupts.

pending_trap: Optional attribute; read/write access; type: Integer.
The exception number of any pending asynchronous trap.

physical_io: Optional attribute; read/write access; type: Object.
I/O space. Must implement both the memory-space and the breakpoint interface.

physical_memory: Required attribute; read/write access; type: Object.
Physical memory space. Must implement both the memory-space and the breakpoint interface.

processor_number: Optional attribute; read/write access; type: Integer.
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.

pstate_mask: Optional attribute; read/write access; type: Integer.
Register pstate bit mask.

reorder_buffer_pop_count: Pseudo attribute; read-only access; type: Integer.
The number of instruction currently in the reorder buffer. Only applicable if the target supports out of order execution.

reorder_buffer_size: Optional attribute; read/write access; type: Integer.
The size of the reorder buffer. Only applicable if the target supports out of order execution.

rstv_address: Optional attribute; read/write access; type: Integer.
The RED_state trap vector base address

simicsfs: Optional attribute; read/write access; type: Object or Nil.
Simicsfs object used to access the host file-system. If set to non NIL, ASR 31 is used by the simicsfs driver to access the simicsfs device.

stall_time: Optional attribute; read/write access; type: Integer.
The number of cycles the processor will stall

stalling_info: Optional attribute; read/write access; type: [iii].
If is_stalling is set, this contains information about the current memory operation.

step_per_cycle_mode: Optional attribute; read/write access; type: String.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.

step_queue: Optional attribute; read/write access; type: [[o|n,a,s,i]*].
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.

step_rate: Optional attribute; read/write access; type: [iii].
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.

steps: Optional attribute; read/write access; type: Integer.
Number steps executed since machine start.

system_tick_frequency: Optional attribute; read/write access; type: Float.
The frequency of the system tick counter in MHz, default is 12.5

time_queue: Optional attribute; read/write access; type: [[o|n,a,s,i]*].
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.

trap_times: Pseudo attribute; read-only access; type: [i*].
List of the time in cycles when a trap has occurred for each trap-level.

turbo_alloc_memory: Session class attribute; read/write access; type: unknown type.
Force allocation of memory.

turbo_block_info: Pseudo class attribute; read/write access; type: unknown type.
Block stats.

turbo_blocks: Pseudo class attribute; read-only access; type: [[iiiii]*].
Compiled blocks.

turbo_code_area: Session class attribute; read-only access; type: unknown type.
Code areas.

turbo_debug_level: Session class attribute; read/write access; type: unknown type.
Turbo engine debug level.

turbo_execution_mode: Session class attribute; read/write access; type: unknown type.
Turbo enable.

turbo_exhaust_current_block: Pseudo class attribute; write-only access; type: unknown type.
Allocate all code space in the current block.

turbo_global_vars: Pseudo class attribute; read-only access; type: unknown type.
Global symbols.

turbo_heap_start: Session class attribute; read-only access; type: unknown type.
Start of heap.

turbo_link_targets: Pseudo class attribute; read-only access; type: unknown type.
Link targets.

turbo_max_compiled_blocks: Session class attribute; read/write access; type: unknown type.
Max number of blocks.

turbo_max_trace_size: Session class attribute; read/write access; type: unknown type.
Max translation unit size.

turbo_processor_offsets: Pseudo class attribute; read-only access; type: unknown type.
Processor offsets.

turbo_register_offsets: Pseudo class attribute; read-only access; type: unknown type.
Register offsets.

turbo_stat: Pseudo class attribute; read/write access; type: unknown type; string indexed; indexed type: unknown type.
Stats.

turbo_stats: Pseudo class attribute; write-only access; type: unknown type.
When set to one, print stats.

turbo_threshold: Session class attribute; read/write access; type: unknown type.
Translation threshold.

turbo_use_direct_sp: Session class attribute; read/write access; type: unknown type.
Direct stack pointer enable.

turbo_use_dstc_direct_lookup: Session class attribute; read/write access; type: unknown type.
Direct DSTC lookup enable.

turbo_use_off_page_chaining: Session class attribute; read/write access; type: unknown type.
Off page chaining enable.

windowed_registers: Optional attribute; read/write access; type: [[i{16}]*].
List of all window registers.

Command List

Commands defined by interface log_object: log, log-group, log-level, log-size, log-type
Commands defined by interface sparc_v9: list-asis, pregs-fpu
Commands defined by interface processor: add-memory-profiler, aprof-views, attach-branch-recorder, break-cr, cycle-break, cycle-break-absolute, detach-branch-recorder, disable, disassemble, down, enable, frame, info, instruction-fetch-mode, io-read, io-write, list, list-memory-profilers, load-binary, logical-to-physical, pos, pregs, pregs-hyper, print-statistics, print-time, psym, read, read-reg, register-number, remove-memory-profiler, set-context, set-pc, stack-trace, start-instruction-profiling, step-break, step-break-absolute, sum, symval, trace-cr, unbreak-cr, untrace-cr, up, wait-for-cycle, wait-for-step, write, write-reg, x

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