The Instruction Set
You should be able to figure out the details of the instruction set for our sample architecture for yourself by now. That being said, you have enough details to worry about already, so I'll give you a brief description of the opcodes [PS] [PDF].
Tracing Internal Signals
Usually, when creating circuits, you just trace the circuit's ports from the testbench. It's also possible to watch signals inside of the circuit. They are addressed almost like files on a hard drive.
For example, I have been tracing my CPU directly (you don't need a testbench if you're not changing the input ports) with the command vhdlsim cpu.
In the CPU, I have instantiated my datapath with
DP: entity work.dp port map ( ... );
(The important part is the DP label.) In the datapath, I have instantiated the register file with the label REGFILE.
If you look at the code for the register file, you'll see that the signal registers is holding the data from each of the registers.
So (after that long setup), I can keep track of the contents of register 0 by putting this line in my sim.scr file
trace /cpu/DP/REGFILE/registers(0)
If I had used a testbench, I could have used a line like
trace /tb_cpu/UUT/DP/REGFILE/registers(0)
Similarly, I can keep track of the program counter by tracing
trace /cpu/CO/PC/data
Doing this can help you figure out if the whole circuit is doing what you expect. More importantly, it can help you track down the problem if it isn't working properly.