CMPT 250 Assignment 3

Due March 10, 2004.

In this assignment, we will finish assembling the example single-cycle architecture from the textbook.

Below is an overview of the construction of the CPU: [figure in PDF]

The green components have been constructed as part of assignments 1 and 2. You can use your own implementations or get the ones from the solutions. The yellow components will be given for this assignment. You should use the provided implementations.

The pink components will be constructed for this assignment, as described below.

A few hints for this assignment have been provided.

On all assignments, there will be marks allocated for the style of your code. You should just make sure you use appropriate variable/signal names, comment hard-to-understand parts, etc.

Datapath

In a file named dp.vhd create a structural description of the datapath for the sample single-cycle architecture. You should use this entity declaration:

entity dp is
  port (
    clock, RW, MB, MD  : in std_logic;
    DA, AA, BA         : in std_logic_vector(2 downto 0);
    FS                 : in std_logic_vector(4 downto 0);
    const_in, data_in  : in std_logic_vector(15 downto 0);
    V, C, N, Z         : out std_logic;
    addr_out, data_out : out std_logic_vector(15 downto 0));
end dp;

You can see the diagrams in Chapter 8 and descriptions in previous assignments for details.

You can use either your own implementation or the one from the solutions for the multiplexer, logic unit and B-input logic.

You can use the provided implementations of the processor status register, register file, ALU, function unit. The adder and shifter are implemented behaviourally in the ALU and function unit that have been provided, so you don't need separate file for them.

Control Unit

In a file named control.vhd create a structural description of the control unit for the sample single-cycle architecture. You should use this entity declaration:

entity control is
  port (
    clock, V, C, N, Z : in std_logic;
    DA, AA, BA, const : out std_logic_vector(2 downto 0);
    FS                : out std_logic_vector(4 downto 0);
    MB, MD, RW, MW    : out std_logic);
end control;

You can see the diagrams in Chapter 7 and descriptions in previous assignments for details.

You can use either your own implementation or the one from the solutions for the sign extender, branch control, program counter and instruction decoder.

You can use the provided implementations of the instruction ROM.

The instruction ROM, is what will really determine the behaviour of the control unit. The provided ROM does a few simple instructions that are described (in assembly) in the VHDL implementation.

CPU

In a file named cpu.vhd create a structural description of the sample single-cycle architecture. You should use this entity declaration:

entity cpu is
  port (
    data_in      : in std_logic_vector(15 downto 0);
    A_out, B_out : out std_logic_vector(15 downto 0);
    MW           : out std_logic);
end cpu;

You can see the diagrams in Chapters 7 and 8 for details.

You can use either your own implementation or the one from the solutions for the zero fill.

You can use the provided implementations of the clock circuit. The clock circuit should be connected to the clock input of the control and datapath, thus providing a common clock signal for the whole CPU.

As you can see, we won't be connecting any data memory to our processor. We can use the outputs and inputs in the simulation to keep an eye on what our processor is doing.

Program It

Make a copy of the provided instruction ROM named instrrom2.vhd (the entity should still be named instrrom). Modify it so it contains a program that adds up the numbers 1, 2, ..., 10 with the following algorithm:

1. put 10₁₀ into R0
2. put 0 into R1
3. while R0>0 do
   1. add R0 to R1
   2. decrement R0
4. store R1 in M[R0] (This isn't really going to happen since we don't have a memory unit, but it will let you see the values of R0, R1 on the A and B output lines, without changing the registers.)

When the program is finished, you should have 0 in R0 and 55₁₀ = 37₁₆ in R1.

You should not use the data input for the CPU. With your instruction ROM included, you should be able to simulate the CPU without a test bench and have it function correctly.

That means you can't do the first step in one instruction since you can't use the constant input and 10 can't be an immediate value (it's only 3 bits).

Submitting

You have to use the Submission server to submit your work. You should submit the files dp.vhd, control.vhd, cpu.vhd, instrrom2.vhd.

You can do this by typing these commands (change into your assignment directory if you haven't already):

tar cvf a3.tar  dp.vhd control.vhd cpu.vhd instrrom2.vhd
gzip a3.tar

Then, submit the file a3.tar.gz. If you want to submit a ZIP file instead, you can do that but figuring out how is your problem.