All the instructions for installing the following software are all available from their web sites; however, I'll include them here:
- For compiling, use Simili.
- For simulating, use Visibly
- You can use (the IDE) Simtool V1.0.9 to add a graphical interface to the VHDL Simili so that you don't have to bother typing all the commands for Simili.
- However, in order to use Visibly and Simtool, you have to install ActiveTcl 8.3.4.2 first.
For simulating using Visibly, following the other instuctions is just fine. However, if you do want to simulate only one input and one output component, such as a NOT gate, then you have to add in another "dummy" signal to the testbench file (ie. add a signal called C in the signal declaration statement, and for file.cmd, add in this: "add list C", without the quotes ).
Also, a tip for using Simtool (the IDE), if one doesn't want to type in
vhdle MYENTITY -do file.cmd -list signal.lst all the time, one can write
it in a script file, (*.do). So everytime one wants to generate the list
file for Visibly to simulate, he/she can simply press the "run script"
button.