std_logic_vector type
The std_logic_vector type is used for arrays of std_logic variables and signals.
The basic VHDL logic operations are defined on this type:
and,
nand,
or,
nor,
xor,
xnor.
These must be given two arrays of the same size; they do the operation on ecah position and return another array. The not operation negates each position in the array.
signal s1, s2, s3 : std_logic_vector(3 downto 0); ... s1(0) <= '0'; s1(1) <= '1'; s1(2) <= '1'; s1(3) <= '0'; s2 <= "1100"; -- sets s(3),s(2) to '1', s(1),s(0) to '0': same order as range in declaration s3 <= s2 -- copies all of s2 into s3 s3 <= s1 and s2; -- "0100"