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timing_model

Implemented By

consistency-controller, g-cache, g-cache-ooo, id-splitter, pci-bus, pcie-switch, perfanalyze, sample-memhier, state-assertion, trace-mem-hier, trans-sorter, trans-splitter, trans-splitter-ooo, trans-staller

Description

The timing-model interface is used to communicate stall times for memory accesses. It is typically exported by cache models. The operate() function is then called on every memory access that misses in the STC, and the return value from the call is the number of cycles to stall.

The snoop-memory interface has the exact same layout as the timing-model interface, but its operate() function is called after the memory access has been performed. The return value from the operate() function of a snoop-memory interface is ignored.

See the Creating a Timing Model chapter in the Simics User Guide for more information on how to use these interfaces.

typedef cycles_t (*operate_func_t)(conf_object_t *NOTNULL mem_hier,
                                   conf_object_t *NOTNULL space,
                                   map_list_t *NOTNULL map_list,
                                   generic_transaction_t *NOTNULL mem_op);

typedef struct timing_model_interface {
        operate_func_t operate;
} timing_model_interface_t;

typedef struct snoop_memory_interface {
        operate_func_t operate;
} snoop_memory_interface_t;

#define TIMING_MODEL_INTERFACE "timing_model"
#define SNOOP_MEMORY_INTERFACE "snoop_memory"

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