An address profile iterator will iterate over a specified portion of the address space in some unspecified order, and return every nonzero counter value exactly once. When done, it will return 0.
struct attr_value {
attr_kind_t kind;
union {
const char *string; /* Sim_Val_String */
integer_t integer; /* Sim_Val_Integer */
integer_t boolean; /* Sim_Val_Boolean */
double floating; /* Sim_Val_Floating */
attr_list_t list; /* Sim_Val_List */
attr_dict_t dict; /* Sim_Val_Dict */
attr_data_t data; /* Sim_Val_Data */
conf_object_t *object; /* Sim_Val_Object */
} u;
};
typedef struct attr_value attr_value_t;
typedef enum {
Sim_Val_Invalid = 0,
Sim_Val_String = 1,
Sim_Val_Integer = 2,
Sim_Val_Floating = 3,
Sim_Val_List = 4,
Sim_Val_Data = 5,
Sim_Val_Nil = 6,
Sim_Val_Object = 7,
Sim_Val_Dict = 8,
Sim_Val_Boolean = 9
} attr_kind_t;
typedef struct attr_list attr_list_t;
struct attr_list {
integer_t size;
struct attr_value *vector; /* [size] */
};
typedef struct {
integer_t size;
struct attr_dict_pair *vector; /* [size] */
} attr_dict_t;
typedef struct attr_dict_pair attr_dict_pair_t;
struct attr_dict_pair {
struct attr_value key;
struct attr_value value;
};
typedef struct attr_data attr_data_t;
struct attr_data {
integer_t size;
uint8 *data; /* [size] */
};
The following table shows how the different types of values are to be interpreted in C and Python, respectively:
| Kind | C | Python |
| Sim_Val_Invalid | n/a | raises exception |
| Sim_Val_String | const char * | String |
| Sim_Val_Integer | integer_t | Integer |
| Sim_Val_Boolean | integer_t | Bool |
| Sim_Val_Floating | double | Float |
| Sim_Val_List | attr_list_t | List |
| Sim_Val_Dict | attr_dict_t | Dictionary |
| Sim_Val_Data | attr_data_t | Tuple |
| Sim_Val_Nil | n/a | None |
Use the SIM_make_attr_XXX functions to create these data types.
typedef enum {
Sim_Class_Kind_Vanilla, /* object is saved at checkpoints */
Sim_Class_Kind_Session, /* object is saved as part of a
* session only */
Sim_Class_Kind_Pseudo /* object is never saved */
} class_kind_t;
typedef struct class_data {
conf_object_t *(*new_instance)(parse_object_t *parse_obj);
int (*delete_instance)(conf_object_t *obj);
void (*finalize_instance)(conf_object_t *obj);
attr_value_t (*default_get_attr)(const char *name,
conf_object_t *obj,
attr_value_t *idx);
set_error_t (*default_set_attr)(const char *name,
conf_object_t *obj,
attr_value_t *val,
attr_value_t *idx);
conf_class_t *parent;
const char *description;
class_kind_t kind;
} class_data_t;
struct conf_object {
conf_class_t *class_data; /* class data */
const char *name; /* instance name */
struct conf_object *queue; /* queue */
lang_void *object_data; /* internal to class implementation */
int object_id; /* deprecated, do not use */
int configured; /* set when configuration ready */
};
typedef struct conf_object conf_object_t;
typedef enum {
Sim_DI_Instruction = 0,
Sim_DI_Data = 1
} data_or_instr_t;
typedef struct dbuffer dbuffer_t;
typedef enum {
Sim_Endian_Target,
Sim_Endian_Host_From_BE,
Sim_Endian_Host_From_LE,
Sim_Endian_Host /* Obsolete. Do not use */
} endianness_t;
typedef void (*event_handler_t)(conf_object_t *obj,
lang_void *parameter);
typedef event_handler_t event_function_t;
typedef int exception_type_t;
struct generic_transaction {
logical_address_t logical_address;
physical_address_t physical_address;
unsigned int size; /* size in bytes */
mem_op_type_t type; /* opaque */
unsigned int atomic:1; /* trans is part of an atomic
sequence of mem ops */
unsigned int inquiry:1; /* set to 1 to indicate inquiry
access */
unsigned int speculative:1; /* access is speculative,
may not be committed */
unsigned int ignore:1; /* set to 1 to signal no-op
(don't do access) */
unsigned int may_stall:1; /* when set to 0, any stall time
returned is ignored */
unsigned int ma_no_reissue:1; /* if the transaction's
instruction is rolled back
during a stall the memory
hierarchy should not be called
again */
unsigned int reissue:1; /* If this is 1, the transaction
will be reissued if a stall
greater than 0 is returned */
unsigned int block_STC:1; /* set to 1 iff anybody (MMU,
memory hierarchy, etc) wants
to see future accesses of this
type */
unsigned int use_page_cache:1; /* internal - do not change */
unsigned int inverse_endian:1; /* data transfer is
byte-reversed */
unsigned int page_cross:2; /* page crossing
0 - no crossing
1 - first access
2 - second access */
unsigned int use_iostc:1; /* may be added to iostc */
unsigned int iostc_blocked:1; /* was blocked from iostc */
ini_type_t ini_type; /* cpu, device, or other */
conf_object_t *ini_ptr;
int id; /* will be different for
simultaneously outstanding
transactions */
exception_type_t exception; /* set if memhier throws
exception, otherwise
Sim_PE_No_Exception */
void *user_ptr; /* user pointer that Simics never
touches */
char *real_address; /* data pointer for the
initiator */
int space_count; /* internal, # of memory space
transitions */
page_t *page; /* internal: page if RAM access */
page_t *tag_page; /* internal: tag page if any */
unsigned tag_page_ofs; /* internal: start of page in tag page */
physical_address_t source_physical_address; /* if arc_type
== Arc_Taken_Branch */
arc_type_t arc_type; /* filled for fetches from
branch targets */
int allocation_size; /* The size of the transaction
(including local part) only
valid if > 0 */
stall_id_t stall_id;
};
typedef struct generic_transaction generic_transaction_t;
typedef enum {
/* Arc caused by a regular branch instruction. */
Arc_None,
Arc_Taken_Branch,
Arc_Init,
Arc_Cache_Line_Start,
Arc_User,
Arc_Compensate,
Arc_Interrupt,
Arc_Page_Start,
/* Arm */
/* Arc caused by a software interrupt instruction. */
Arc_Exception_Counted,
/* Arc caused by some other exception than software interrupt. This
kind of branch arc is special in that it is not subtracted from the
number of times the instruction has been executed. */
Arc_Exception_Not_Counted,
/* Arc caused by an ALU instruction with pc as rd and the s bit set,
i.e, probably a return from an exception. */
Arc_Return_From_Exception,
/* Arc caused by the execution entering or leaving the interpreter. */
Arc_To_From_Interpreter,
/* Arc caused by a fall through from one storage page to the next. */
Arc_End_Of_Page,
/* Just to avoid comma problems with the ifdefs... */
Arc_Dummy
} arc_type_t;
typedef struct page page_t;
The transaction parameters are divided into a generic part shown below and an architecture specific part. The generic struct is included as the first component of the memory_transaction_t struct, where the architecture-specific parameters are declared.
Normally the logical address and most control flags are set before the mmu is called. The host_address is a host pointer to the start of the simulated memory the transaction loads from or stores to.
real_address points to the destination for a load or source of a store operation.
The ini_ptr points to the object initiating the operation, this is
either a processor or a device depending on the ini_type field.
typedef enum {
Sim_Initiator_Illegal = 0x0, /* catch uninitialized */
Sim_Initiator_CPU = 0x1000,
Sim_Initiator_CPU_V9 = 0x1100,
Sim_Initiator_CPU_UII = 0x1101,
Sim_Initiator_CPU_UIII = 0x1102,
Sim_Initiator_CPU_UIV = 0x1103,
Sim_Initiator_CPU_UT1 = 0x1104, /* 1105, 1106 internal */
Sim_Initiator_CPU_X86 = 0x1200,
Sim_Initiator_CPU_PPC = 0x1300,
Sim_Initiator_CPU_Alpha = 0x1400,
Sim_Initiator_CPU_IA64 = 0x1500,
Sim_Initiator_CPU_MIPS = 0x1600,
Sim_Initiator_CPU_MIPS_RM7000 = 0x1601,
Sim_Initiator_CPU_MIPS_E9000 = 0x1602,
Sim_Initiator_CPU_ARM = 0x1700,
Sim_Initiator_Device = 0x2000,
Sim_Initiator_PCI_Device = 0x2010,
Sim_Initiator_Cache = 0x3000, /* The transaction is a cache
transaction as defined by
g-cache */
Sim_Initiator_Other = 0x4000 /* initiator == NULL */
} ini_type_t;
The mmu sets the physical_address and possibly set some more control flags. The memory hierarchy only reads the memory transaction to decide what stall time to return.
The block_STC bit functions as a "veto" flag for various modules. Any code can set this to 1, but it should not be set to zero. When set to one, the next access to the same STC line will be passed to the memory hierarchy.
The may_stall bit is set to zero for a few types of references where the simulator kernel cannot deal with stalling. A memory hierarchy must return stall time zero when the flag is clear. A memory hierarchy that wants to stall anyway should accumulate stall time, and trigger the total stall time when a stall-capable access comes along (which is not guaranteed to happen but most probably will). For atomic read/write instructions (swap) any access may stall. If an instruction is stalled the entire instruction will be executed after the stalltime is up. The may_stall bit may be cleared by the mmu.
The ignore flag can be set to 1 by the MMU. When set no memory operation will be performed. This is useful for instructions coded as a memory operation but which really only modify mmu internal state.
The inverse_endian flag may be changed by the MMU. If set, the data involved in the access will be transferred in the opposite order. If not set, the bytes will be transferred in the same order they occur in the memory space. A memory object should not set this bit to a hard value, only toggle it. It may have been set by Simics for implementation reasons.
The page_cross field is used to indicate when Simics has split a memory transaction in two. It is normally 0, but when a transaction crosses an MMU page boundary, it will be converted into two separate transactions, one for each accessed page. The addresses and sizes are adjusted to confine them to their respective pages. The first of these transaction will have page_cross set to 1, and the second will have it set to 2.
The atomic is read only. It may be read by any module. The atomic flag is set for any data memory transaction caused by an atomic instruction; i.e., an instruction whose memory references must be performed without any intervening memory references (from other processors). The atomic sequence is a read followed by a write.
The use_page_cache is used internally. Do not change its value.
The user_ptr may be used to pass information between user defined modules that use memory transactions. Simics does not use this field.
The type field should not be used directly; use the SIM_mem_op_is_xxx() predicate functions, where xxx can be instruction, data, read, or write. SIM_set_mem_op_type() function is used to set the type of a memory operation (see the mem_op_type_t enum definition), and SIM_get_mem_op_type() is used to read it.
id is a unique number for all currently outstanding memory transactions. In an in-order version of Simics, this field is zero. See the SIM_get_unique_memory_transaction_id() function.
When activated, instruction fetches set arc_type to indicate if the fetch is the result of sequential execution or a branch. In case of a branch, the source_physical_address is set to the address where the branch was made from.
typedef enum {
Sim_Hap_Simulation = 1,
Sim_Hap_Old_Format = 2, /* internal use */
Sim_Hap_Added = 4, /* internal use */
Sim_Hap_Deleted = 8, /* internal use */
Sim_Hap_Attr = 16 /* internal use */
} hap_flags_t;
typedef int hap_type_t;
typedef uint64 instr_type_t;
#define It_Other UINT64_C(0x1)
#define It_Alu UINT64_C(0x2)
#define It_Relbranch UINT64_C(0x4)
#define It_Load UINT64_C(0x8)
#define It_Store UINT64_C(0x10)
#define It_Sethi UINT64_C(0x20)
#define It_Popc UINT64_C(0x40)
#define It_Fp_Triop UINT64_C(0x80)
#define It_Fp_Diop UINT64_C(0x100)
#define It_Fp_Unop UINT64_C(0x200)
#define It_Fp_Cmp UINT64_C(0x400)
#define It_Swap UINT64_C(0x800)
#define It_Vis UINT64_C(0x1000)
#define It_Flush UINT64_C(0x2000)
#define It_Call UINT64_C(0x4000)
#define It_Return UINT64_C(0x8000)
#define It_Trap UINT64_C(0x10000)
#define It_Trap_Ret UINT64_C(0x20000)
#define It_Idle UINT64_C(0x40000)
#define It_User_Decoder_Defined UINT64_C(0x80000)
#define It_Varbranch UINT64_C(0x100000) /* Branchtarget is dynamic */
#define It_Absbranch UINT64_C(0x200000) /* branch to an immidiate absolute target */
#define It_Fstsw UINT64_C(0x400000) /* fstsw */
#define It_Fp UINT64_C(0x800000) /* floating point instruction */
#define It_Membar UINT64_C(0x1000000)
#define It_Prefetch UINT64_C(0x2000000)
#define It_Convert UINT64_C(0x4000000)
#define It_Cmov UINT64_C(0x8000000)
#define It_String UINT64_C(0x10000000)
#define It_Mov UINT64_C(0x20000000)
#define It_SSE UINT64_C(0x40000000)
#define It_MMX UINT64_C(0x80000000)
#define It_Cond UINT64_C(0x100000000) /* Conditional, i.e it may continue to
the sequentially next instruction */
typedef enum instruction_error {
Sim_IE_OK = 0,
Sim_IE_Unresolved_Dependencies,
Sim_IE_Speculative,
Sim_IE_Stalling,
Sim_IE_Not_Inserted, /* trying to execute or squash an
instruction that is inserted. */
Sim_IE_Exception, /* (SPARC-V9 only) */
Sim_IE_Fault = Sim_IE_Exception,
Sim_IE_Trap, /* (X86 only) Returned if a trap is
encountered */
Sim_IE_Interrupt, /* (X86 only) Returned if an interrupt is
waiting and interrupts are enabled */
Sim_IE_Sync_Instruction, /* Returned if sync instruction is
not allowd to execute */
Sim_IE_No_Exception, /* Returned by SIM_instruction_
handle_exception */
Sim_IE_Illegal_Interrupt_Point,
Sim_IE_Illegal_Exception_Point,
Sim_IE_Illegal_Address,
Sim_IE_Illegal_Phase,
Sim_IE_Interrupts_Disabled,
Sim_IE_Illegal_Id,
Sim_IE_Instruction_Tree_Full,
Sim_IE_Null_Pointer,
Sim_IE_Illegal_Reg,
Sim_IE_Invalid,
Sim_IE_Out_of_Order_Commit,
Sim_IE_Retired_Instruction, /* try to squash a retiring instruction */
Sim_IE_Not_Committed, /* Returned by SIM_instruction_end */
Sim_IE_Code_Breakpoint,
Sim_IE_Mem_Breakpoint,
Sim_IE_Step_Breakpoint,
Sim_IE_Hap_Breakpoint
} instruction_error_t;
typedef enum instruction_phase {
Sim_Phase_Initiated,
Sim_Phase_Fetched,
Sim_Phase_Decoded,
Sim_Phase_Executed,
Sim_Phase_Retired,
Sim_Phase_Committed,
Sim_Phases
} instruction_phase_t;
typedef enum {
Sim_IS_Waiting = 0x1, /* Not all inputs are ready */
Sim_IS_Ready = 0x2, /* All inputs are ready */
Sim_IS_Stalling = 0x4, /* Waiting for memory to
finish the operation */
Sim_IS_Executed = 0x8, /* Done */
Sim_IS_Faulting = 0x10, /* Has raised an exception -
a fault in x86 case */
Sim_IS_Branch_Taken = 0x20, /* The branch is taken for
branch instructions */
Sim_IS_Trap = 0x40, /* (x86) this instruction
generated a trap */
Sim_IS_Interrupt = 0x80, /* (x86) this instruction can not
be executed because the interrupt
must be taken first */
Sim_IS_Retired = 0x100 /* All stores are retired */
} instruction_status_t;
The intn types are defined to be signed integers of exactly n bits. The uintn types are their unsigned counterparts.
intptr_t and uintptr_t are signed and unsigned integer types of a size that lets any pointer to void be cast to it and then cast back to a pointer to void, and the result will compare equal to the original pointer. This typically means that the two types are 32 bits wide on 32-bit machines and 64 bits on 64-bit machines.
integer_t and uinteger_t are the largest integers (signed and unsigned, respectively) used by the Simics API. They are currently defined to be 64 bits.
typedef void lang_void;
typedef void typed_lang_void;
Typically, this is used by iterator functions in the API which take callback functions as arguments. The callback function is later called with the lang_void data and the object being iterated over.
struct log_object {
conf_object_t obj;
uint32 access_cnt; /* number of IO transactions
* performed */
int access_active; /* set while an access is in
* progress */
io_trace_log_t *active_trace; /* temporary log list during
* the access */
io_trace_t *trace_buffer;
int trace_next;
int trace_wrap;
int trace_size;
int log_level;
int group_mask;
int type_mask;
};
typedef struct log_object log_object_t;
Since the internal representation of this structure may change between releases, classes using the structure should not inspect the members directly (except for obj), but rather use the attributes. New entries should be added with the SIM_log_message() function. From C/C++ the SIM_log_... helper functions are recommended.
typedef enum {
Sim_Log_Info, // Normal informational message
Sim_Log_Error, // Simics error
Sim_Log_Undefined, // use of undefined target behavior
Sim_Log_Spec_Violation, // target program violates the specification
Sim_Log_Target_Error, // error state in target (not in Simics)
Sim_Log_Unimplemented, // not implemented in Simics
Sim_Log_Num_Types // Do not use
} log_type_t;
logical_address_t is an unsigned integer sufficiently large to contain logical (virtual) addresses on the target machine. define.
physical_address_t is an unsigned integer sufficiently large to contain physical addresses on the target machine.
generic_address_t is defined to be the largest of the logical_address_t and physical_address_t types.
linear_address_t is used for linear addresses used on x86 machines after segmentation but before paging.
typedef struct map_info {
physical_address_t base;
physical_address_t start;
physical_address_t length;
int function;
uint8 priority;
int align_size;
swap_mode_t reverse_endian;
} map_info_t;
typedef enum swap_mode {
Sim_Swap_None = 0,
Sim_Swap_Bus = 1,
Sim_Swap_Bus_Trans = 2,
Sim_Swap_Trans = 3
} swap_mode_t;
typedef enum {
Sim_Map_Ram,
Sim_Map_Rom,
Sim_Map_IO,
Sim_Map_Port,
Sim_Map_Translate = 0x100, /* pseudo - do not use */
Sim_Map_Translate_To_Space,
Sim_Map_Translate_To_Ram,
Sim_Map_Translate_To_Rom
} map_type_t;
struct map_list {
map_type_t map_type;
conf_object_t *object;
void *interface_ptr;
void *target_interface;
void *breakpoint_interface;
void *bridge_interface;
conf_object_t *target_object;
conf_object_t *bridge;
map_info_t map_info;
physical_address_t map_size; /* not constant, use with caution */
int deleted; /* internal flag - should always be 0 ! */
};
typedef struct map_list map_list_t;
typedef enum {
Sim_Trans_Load = 0,
Sim_Trans_Store = Sim_Trn_Write,
Sim_Trans_Instr_Fetch = Sim_Trn_Instr,
Sim_Trans_Prefetch = Sim_Trn_Prefetch | Sim_Trn_Control,
Sim_Trans_Cache = Sim_Trn_Control
} mem_op_type_t;
typedef struct pci_memory_transaction {
generic_transaction_t s;
/* The original_size field will probably be moved to the
generic_transaction_t structure in the future */
uint32 original_size;
int bus_address;
} pci_memory_transaction_t;
typedef enum {
Sim_CPU_Mode_User = 0,
Sim_CPU_Mode_Supervisor = 1,
Sim_CPU_Mode_Hypervisor
} processor_mode_t;
typedef struct conf_object processor_t;
typedef enum {
Sim_PE_No_Exception = 1025,
Sim_PE_Code_Break,
Sim_PE_Silent_Break,
Sim_PE_Inquiry_Outside_Memory,
Sim_PE_Inquiry_Unhandled,
Sim_PE_IO_Not_Taken,
Sim_PE_IO_Error,
Sim_PE_Interrupt_Break,
Sim_PE_Interrupt_Break_Take_Now,
Sim_PE_Exception_Break,
Sim_PE_Hap_Exception_Break,
Sim_PE_Stall_Cpu,
Sim_PE_Locked_Memory,
Sim_PE_Return_Break,
Sim_PE_Instruction_Finished,
Sim_PE_Default_Semantics,
Sim_PE_Ignore_Semantics,
Sim_PE_Speculation_Failed,
Sim_PE_Invalid_Address,
Sim_PE_MAI_Return,
Sim_PE_Last
} pseudo_exceptions_t;
typedef enum {
Sim_RW_Read = 0,
Sim_RW_Write = 1
} read_or_write_t;
typedef enum {
Sim_Reg_Type_Invalid,
Sim_Reg_Type_Integer,
Sim_Reg_Type_Floating,
Sim_Reg_Type_Control
} register_type_t;
typedef enum {
Sim_Set_Ok,
Sim_Set_Need_Integer,
Sim_Set_Need_Floating,
Sim_Set_Need_String,
Sim_Set_Need_List,
Sim_Set_Need_Dict,
Sim_Set_Need_Boolean,
Sim_Set_Need_Data,
Sim_Set_Need_Object,
Sim_Set_Object_Not_Found,
Sim_Set_Interface_Not_Found,
Sim_Set_Illegal_Value,
Sim_Set_Illegal_Type,
Sim_Set_Illegal_Index,
Sim_Set_Attribute_Not_Found,
Sim_Set_Not_Writable,
Sim_Set_Ignored
} set_error_t;
Sim_Set_Ok
The attribute was successfully set.
Sim_Set_Need_Integer
Sim_Set_Need_Floating
Sim_Set_Need_String
Sim_Set_Need_List
Sim_Set_Need_Dict
Sim_Set_Need_Boolean
Sim_Set_Need_Data
Sim_Set_Need_Object
The value is of an illegal type for the attribute. Deprecated, use
Sim_Set_Illegal_Type instead.
Sim_Set_Object_Not_Found
The string value does not match any object name.?Deprecated, use attributes
of object type instead of string attributes referring to object names.
Sim_Set_Interface_Not_Found
The object value does not implement an interface required by the attribute.
Sim_Set_Illegal_Value
The value is of a legal type for the attribute, but outside the legal range.
Sim_Set_Illegal_Type
The value is of an illegal type for the attribute.
Sim_Set_Attribute_Not_Found
The object has no attribute with the specified name. Should only be returned
by SIM_set_attribute() family of functions, not by attribute set
functions.
Sim_Set_Not_Writable
The attribute is read-only.
Sim_Set_Ignored
The value was accepted for backwards compatibility reasons, but was ignored.
Should only be returned by set_event_info() functions registered
with the event-poster interface.
typedef integer_t simtime_t;
typedef simtime_t cycles_t;
typedef simtime_t pc_step_t;
typedef simtime_t nano_secs_t;
cycles_t is used when the time is specified in cycles, pc_step_t is used when the time is specified in steps, and simtime_t is used in places where it is unknown whether the time is in steps or cycles. See the chapter "The Simics Simulator" in the Simics User Guide for a discussion about the difference between steps and cycles.
nano_secs_t is used to express a number of nanoseconds (10−9 seconds).
#ifdef _WIN32 typedef SOCKET socket_t; #else typedef int socket_t; #endif /* !_WIN32 */
typedef enum {
Sim_Alpha_Mode_Kernel = 0,
Sim_Alpha_Mode_Executive = 1,
Sim_Alpha_Mode_Supervisor = 2,
Sim_Alpha_Mode_User = 3
} alpha_cpu_mode_t;
typedef struct alpha_memory_transaction {
/* generic transaction */
generic_transaction_t s;
/* mode of the current alpha cpu */
int mode;
/* flags used by hw_ld / hw_st instructions */
palcode_memop_flags_t palcode_flags;
/* The pte is needed the Icache module, since it needs the ASM bit. */
uint64 pte;
/* if non-zero, the id needed to calculate the program counter */
intptr_t turbo_miss_id;
} alpha_memory_transaction_t;
The s field contains generic information about memory operations (see generic_transaction_t). The mode is the current mode of the alpha cpu. The values of palcode_flags, used by hw_ld and hw_st instructions, see palcode_memop_flags_t datatype.
typedef struct arm_memory_transaction {
/* generic transaction */
generic_transaction_t s;
/* processor mode */
processor_mode_t mode;
int rotate;
/* if non-zero, the id needed to calculate the program counter */
intptr_t turbo_miss_id;
} arm_memory_transaction_t;
This is the ARM specific memory transaction data structure. The generic data is stored in the s field.
The mode field specifies the processor mode the MMU should assume when processing the transaction. This is the same as the current mode of the processor, except that it is always Sim_CPU_Mode_User for ldrbt, ldrt, strbt and strt instructions.
typedef struct ia64_fp_register {
uint64 significand;
uint32 exponent;
unsigned sign:1;
unsigned nat:1;
} ia64_fp_register_t;
typedef enum {
IA64_Abort_RESET = 1,
IA64_Abort_MCA,
IA64_Int_INIT,
IA64_Int_PMI,
IA64_Int_INT,
IA64_Fault_IR_unimplmented_data_address,
IA64_Fault_IR_data_nested_tlb,
IA64_Fault_IR_alternate_data_tlb,
IA64_Fault_IR_vhpt_data,
IA64_Fault_IR_data_tlb,
IA64_Fault_IR_data_page_not_present,
IA64_Fault_IR_data_nat_page_consumption,
IA64_Fault_IR_data_key_miss,
IA64_Fault_IR_data_key_permission,
IA64_Fault_IR_data_access_rights,
IA64_Fault_IR_data_access_bit,
IA64_Fault_IR_data_debug,
IA64_Fault_IA32_instruction_breakpoint,
IA64_Fault_IA32_code_fetch,
IA64_Fault_alternate_instruction_tlb,
IA64_Fault_vhpt_instruction,
IA64_Fault_instruction_tlb,
IA64_Fault_instruction_page_not_present,
IA64_Fault_instruction_nat_page_consumption,
IA64_Fault_instruction_key_miss,
IA64_Fault_instruction_key_permission,
IA64_Fault_instruction_access_rights,
IA64_Fault_instruction_access_bit,
IA64_Fault_instruction_debug,
IA64_Fault_IA32_instruction_length,
IA64_Fault_IA32_invalid_opcode,
IA64_Fault_IA32_instruction_intercept,
IA64_Fault_illegal_operation,
IA64_Fault_illegal_dependency,
IA64_Fault_break_instruction,
IA64_Fault_privileged_operation,
IA64_Fault_disabled_floating_point_register,
IA64_Fault_diabled_instruction_set_transition,
IA64_Fault_IA32_device_not_available,
IA64_Fault_IA32_fp_error,
IA64_Fault_register_nat_consumption,
IA64_Fault_reserved_register_field,
IA64_Fault_unimplemented_data_address,
IA64_Fault_privileged_register,
IA64_Fault_speculative_operation,
IA64_Fault_IA32_stack_exception,
IA64_Fault_IA32_general_protection,
IA64_Fault_data_nested_tlb,
IA64_Fault_alternate_data_tlb,
IA64_Fault_vhpt_data,
IA64_Fault_data_tlb,
IA64_Fault_data_page_not_present,
IA64_Fault_data_nat_page_consumption,
IA64_Fault_data_key_miss,
IA64_Fault_data_key_permission,
IA64_Fault_data_access_rights,
IA64_Fault_data_dirty_bit,
IA64_Fault_data_access_bit,
IA64_Fault_data_debug,
IA64_Fault_unaligned_data_reference,
IA64_Fault_IA32_alignment_check,
IA64_Fault_IA32_locked_data_reference,
IA64_Fault_IA32_segment_not_present,
IA64_Fault_IA32_divide_by_zero,
IA64_Fault_IA32_bound,
IA64_Fault_IA32_sse_numeric_error,
IA64_Fault_unsupported_data_reference,
IA64_Fault_floating_point,
IA64_Trap_unimplemented_instruction_address,
IA64_Trap_floating_point,
IA64_Trap_lower_privilege_transfer,
IA64_Trap_taken_branch,
IA64_Trap_single_step,
IA64_Trap_IA32_system_flag_intercept,
IA64_Trap_IA32_gate_intercept,
IA64_Trap_IA32_into,
IA64_Trap_IA32_breakpoint,
IA64_Trap_IA32_software_interrupt,
IA64_Trap_IA32_data_breakpoint,
IA64_Trap_IA32_taken_branch,
IA64_Trap_IA32_single_step
} ia64_interruption_t;
typedef enum {
IT_abort,
IT_interrupt,
IT_fault,
IT_trap
} ia64_interruption_type_t;
typedef enum {
IVA_vhpt_trans = 0x0000,
IVA_instr_tlb = 0x0400,
IVA_data_tlb = 0x0800,
IVA_alt_instr_tlb = 0x0c00,
IVA_alt_data_tlb = 0x1000,
IVA_data_nested = 0x1400,
IVA_instr_key_miss = 0x1800,
IVA_data_key_miss = 0x1c00,
IVA_dirty_bit = 0x2000,
IVA_instr_acc_bit = 0x2400,
IVA_data_acc_bit = 0x2800,
IVA_break = 0x2c00,
IVA_ext_int = 0x3000,
IVA_page_not_pres = 0x5000,
IVA_key_perm = 0x5100,
IVA_instr_acc_right = 0x5200,
IVA_data_acc_right = 0x5300,
IVA_gen_exc = 0x5400,
IVA_dis_fp = 0x5500,
IVA_nat_cons = 0x5600,
IVA_spec = 0x5700,
IVA_debug = 0x5900,
IVA_unal_ref = 0x5a00,
IVA_unsup_data_ref = 0x5b00,
IVA_fp = 0x5c00,
IVA_fp_trap = 0x5d00,
IVA_lp_trans_trap = 0x5e00,
IVA_tak_br_trap = 0x5f00,
IVA_ss_trap = 0x6000,
IVA_ia32_exc = 0x6900,
IVA_ia32_intercept = 0x6a00,
IVA_ia32_interrupt = 0x9b00
} ia64_iva_offset_t;
typedef struct ia64_memory_transaction {
/* generic transaction */
generic_transaction_t s;
int privilege_level;
int speculative;
int advanced;
int non_access;
uint16 isr_code;
int rse;
int rse_ir;
/* "Output" */
int deferred_fault;
} ia64_memory_transaction_t;
The privilege_level is the current privilege level (0-3) of the cpu.
The speculative flag indicates that the memory operation is caused by control speculation.
The advanced flag indicates an advanced load, i.e. that the memory operation is caused by data speculation.
The isr_code is used to help the MMU fill in the correct values in the cr.isr register on a fault.
The rse flag indicates that the memory operation is caused by a mandatory RSE operation, and the rse_ir whether the current frame is incomplete. This is used to raise the appropriate faults on failure.
The deferred_fault is set by the MMU when a speculative memory operation fails.
typedef struct mips_memory_transaction {
/* generic transaction */
generic_transaction_t s;
/* Cache coherency, values as the C field in EntryLo0 and EntryLo1. */
unsigned int cache_coherency:3;
/* if non-zero, the id needed to calculate the program counter */
intptr_t turbo_miss_id;
} mips_memory_transaction_t;
This is the MIPS specific memory transaction data structure. The generic data is stored in the s field.
The cache_coherency field specifies the cache coherency attribute of the memory transaction, as defined by the C field of the EntryLo0 and EntryLo1 coprocessor 0 registers.
typedef enum palcode_memop_flags {
/* nothing special */
Pal_memop_normal = 0x0000,
/* cleared: the effective address is virtual
set: the effective address is physical */
Pal_memop_physical = 0x0001,
/* cleared: use current mode for access checks
set: use alt mode for access checks */
Pal_memop_altmode = 0x0002,
/* cleared: check fault-on-read (FOR) and read access violations
set: check FOR, fault-on-write and read/write violations */
Pal_memop_wrtck = 0x0004,
/* cleared: length is longword
set: length is quadword */
Pal_memop_quadword = 0x0008,
/* cleared: normal fetch
set: flags a virtual pte fetch */
Pal_memop_vpte = 0x0010,
/* cleared: normal operation
set: load-locked version of hw_ld */
Pal_memop_lock = 0x0020,
/* cleared: normal operation
set: store-conditional version of hw_st */
Pal_memop_cond = 0x0040
} palcode_memop_flags_t;
typedef enum {
/* Normal load or store instructions */
Normal_Load_Store = 0,
/* No data touched by the load/store will be placed in cache */
Caching_Inhibited,
Instr_Multiple, /* load/store multiple */
Instr_String, /* load/store string */
Instr_Altivec_Element, /* Altivec load/store element */
/* Data cache manipulations */
Instr_dcbt, /* data cache block touch */
Instr_dcbst, /* data cache block store */
Instr_dcbtst, /* data cache block touch for store */
Instr_dcbi, /* data cache block invalidate */
Instr_dcbf, /* data cache block flush */
Instr_dcbfl, /* data cache block flush local */
Instr_dcba, /* data cache block allocate */
Instr_dcbz, /* data cache block to zero */
/* Instruction cache manipulations */
Instr_icbi, /* instruction cache block invalidate */
/* Data stream (Altivec) manipulations */
Instr_dst, /* data stream touch */
Instr_dstt, /* data stream touch transient */
Instr_dstst, /* data stream touch for store */
Instr_dststt, /* data stream touch for store transient */
/* e500 cache lock apu instructions */
Instr_dcblc_l1, /* data cache block lock clear (L1) */
Instr_dcblc_l2, /* data cache block lock clear (L2) */
Instr_dcbtls_l1, /* data cache block touch and lock set (L1)*/
Instr_dcbtls_l2, /* data cache block touch and lock set (L1)*/
Instr_dcbtstls_l1, /* data cache block touch for store and lock
set (L1)*/
Instr_dcbtstls_l2, /* data cache block touch for store and lock
set (L1)*/
Instr_icblc_l1, /* instruction cache block clear (L1) */
Instr_icblc_l2, /* instruction cache block clear (L2) */
Instr_icbtls_l1, /* instruction cache block touch and lock
set (L1) */
Instr_icbtls_l2, /* instruction cache block touch and lock
set (L1) */
/* Other loads/stores or cache affecting instructions */
Instr_lwarx,
Instr_stwcx,
Instr_ldarx,
Instr_stdcx,
Instr_lq,
Instr_stq,
/* Other cache affecting instructions */
Instr_sync,
Instr_eieio,
Instr_ecowx,
Instr_eciwx,
Instr_tlbie,
Instr_tlbsync,
Instr_isync,
Instr_lfdp, /* Load Floating point Double Pair */
Instr_stfdp /* Store Floating point Double Pair */
} ppc_mem_instr_origin_t;
typedef struct ppc_memory_transaction {
/* generic transaction */
generic_transaction_t s;
processor_mode_t mode;
ppc_mem_instr_origin_t instr_origin;
logical_address_t ea_origin;
uint8 wimg;
uint8 alignment;
/* cache operations may flag this to cause prefetches to be no-ops */
uint8 inhibit_exception;
intptr_t turbo_miss_id;
} ppc_memory_transaction_t;
This is the PPC specific memory transaction data structure. The generic data is stored in the s field.
The current processor mode when generating this transaction is stored in the mode field.
The type of instruction generating the memory transactions is provided by the instr_origin field. Note that it is mainly provided for special memory accesses like cache block operations..
The wimg field is filled in by the MMU with the corresponding WIMG bits during the translation.
The alignment field contains the size on which the transaction is required to be aligned.
The inhibit_exception field is set for operations that should be ignored if triggering an exception.
typedef uint32 register_id_t;
typedef enum {
V9_Reg_Id_R0 = 0,
/* R1 - R31 */
V9_Reg_Id_F0 = 32,
/* F1 - F63 */
V9_Reg_Id_FCC0 = 96,
V9_Reg_Id_FCC1 = 97,
V9_Reg_Id_FCC2 = 98,
V9_Reg_Id_FCC3 = 99,
V9_Reg_Id_CC = 100,
V9_Reg_Id_PC = 101,
V9_Reg_Id_NPC = 102,
V9_Reg_Id_AEXC = 103, /* part of fsr */
V9_Reg_Id_CEXC = 104, /* part of fsr */
V9_Reg_Id_FTT = 105, /* part of fsr */
V9_Reg_Id_DUDL = 106, /* part of fprs */
V9_Reg_Id_FEF = 107, /* part of fprs */
V9_Reg_Id_Y = 108,
V9_Reg_Id_GSR = 109,
V9_Reg_Id_CANSAVE = 110,
V9_Reg_Id_CANRESTORE = 111,
V9_Reg_Id_OTHERWIN = 112,
V9_Reg_Id_CLEANWIN = 113,
V9_Reg_Id_CWP = 114,
V9_Reg_Id_ASI = 115,
V9_Reg_Id_Not_Used = 124,
V9_Reg_Id_Sync = 125
} v9_register_id_t;
typedef enum {
X86_Reg_Id_Rax = 0,
X86_Reg_Id_Rcx = 1,
X86_Reg_Id_Rdx = 2,
X86_Reg_Id_Rbx = 3,
X86_Reg_Id_Rsp = 4,
X86_Reg_Id_Rbp = 5,
X86_Reg_Id_Rsi = 6,
X86_Reg_Id_Rdi = 7,
X86_Reg_Id_R8 = 8,
X86_Reg_Id_R9 = 9,
X86_Reg_Id_R10 = 10,
X86_Reg_Id_R11 = 11,
X86_Reg_Id_R12 = 12,
X86_Reg_Id_R13 = 13,
X86_Reg_Id_R14 = 14,
X86_Reg_Id_R15 = 15,
X86_Reg_Id_Xmm0 = 16,
X86_Reg_Id_Xmm1 = 17,
X86_Reg_Id_Xmm2 = 18,
X86_Reg_Id_Xmm3 = 19,
X86_Reg_Id_Xmm4 = 20,
X86_Reg_Id_Xmm5 = 21,
X86_Reg_Id_Xmm6 = 22,
X86_Reg_Id_Xmm7 = 23,
X86_Reg_Id_Xmm8 = 24,
X86_Reg_Id_Xmm9 = 25,
X86_Reg_Id_Xmm10 = 26,
X86_Reg_Id_Xmm11 = 27,
X86_Reg_Id_Xmm12 = 28,
X86_Reg_Id_Xmm13 = 29,
X86_Reg_Id_Xmm14 = 30,
X86_Reg_Id_Xmm15 = 31,
X86_Reg_Id_Mm0 = 32,
X86_Reg_Id_Mm1 = 33,
X86_Reg_Id_Mm2 = 34,
X86_Reg_Id_Mm3 = 35,
X86_Reg_Id_Mm4 = 36,
X86_Reg_Id_Mm5 = 37,
X86_Reg_Id_Mm6 = 38,
X86_Reg_Id_Mm7 = 39,
X86_Reg_Id_PC = 40, /* this is RIP */
X86_Reg_Id_CF = 41, /* integer condition code flags */
X86_Reg_Id_DST = 42, /* DST field used to cache PF flag */
X86_Reg_Id_AF = 43,
X86_Reg_Id_ZF = 44,
X86_Reg_Id_SF = 45,
X86_Reg_Id_OF = 46,
X86_Reg_Id_DF = 47,
X86_Reg_Id_EFLAGS = 48, /* the whole 32 bits eflags */
X86_Reg_Id_C0 = 49, /* floating point cc flags */
X86_Reg_Id_C1 = 50,
X86_Reg_Id_C2 = 51,
X86_Reg_Id_C3 = 52,
X86_Reg_Id_Top = 53, /* floating point stack top */
X86_Reg_Id_Not_Used, /* dummy number that can be used */
X86_Reg_Id_Local_Max /* keep this one last */
} x86_register_id_t;
#define V9_REG_ID_RN(n) (V9_Reg_Id_R0+(n))
#define V9_REG_ID_FN(n) (V9_Reg_Id_F0+(n))
#define V9_REG_ID_FCCN(n) (V9_Reg_Id_FCC0+(n))
typedef enum v9_exception_type {
Power_On_Reset = 0x001,
Watchdog_Reset = 0x002,
Externally_Initiated_Reset = 0x003,
Software_Initiated_Reset = 0x004,
Red_State_Exception = 0x005,
Instruction_Access_Exception = 0x008,
Instruction_Access_MMU_Miss = 0x009,
Instruction_Access_Error = 0x00a,
Illegal_Instruction = 0x010,
Privileged_Opcode = 0x011,
Unimplemented_Ldd = 0x012,
Unimplemented_Std = 0x013,
Fp_Disabled = 0x020,
Fp_Exception_Ieee_754 = 0x021,
Fp_Exception_Other = 0x022,
Tag_Overflow = 0x023,
Clean_Window = 0x024,
Division_By_Zero = 0x028,
Internal_Processor_Error = 0x029,
Data_Access_Exception = 0x030,
Data_Access_MMU_Miss = 0x031,
Data_Access_Error = 0x032,
Data_Access_Protection = 0x033,
Mem_Address_Not_Aligned = 0x034,
Lddf_Mem_Address_Not_Aligned = 0x035,
Stdf_Mem_Address_Not_Aligned = 0x036,
Privileged_Action = 0x037,
Ldqf_Mem_Address_Not_Aligned = 0x038,
Stqf_Mem_Address_Not_Aligned = 0x039,
Async_Data_Error = 0x040,
Interrupt_Level_1 = 0x41,
Interrupt_Level_2 = 0x42,
Interrupt_Level_3 = 0x43,
Interrupt_Level_4 = 0x44,
Interrupt_Level_5 = 0x45,
Interrupt_Level_6 = 0x46,
Interrupt_Level_7 = 0x47,
Interrupt_Level_8 = 0x48,
Interrupt_Level_9 = 0x49,
Interrupt_Level_10 = 0x4a,
Interrupt_Level_11 = 0x4b,
Interrupt_Level_12 = 0x4c,
Interrupt_Level_13 = 0x4d,
Interrupt_Level_14 = 0x4e,
Interrupt_Level_15 = 0x4f,
Interrupt_Vector = 0x60,
PA_Watchpoint = 0x61,
VA_Watchpoint = 0x62,
Corrected_ECC_Error = 0x63,
Fast_Instruction_Access_MMU_Miss = 0x64,
Fast_Data_Access_MMU_Miss = 0x68,
Fast_Data_Access_Protection = 0x6c,
Fast_ECC_Error = 0x70,
Spill_0_Normal = 0x080,
Spill_1_Normal = 0x084,
Spill_2_Normal = 0x088,
Spill_3_Normal = 0x08c,
Spill_4_Normal = 0x090,
Spill_5_Normal = 0x094,
Spill_6_Normal = 0x098,
Spill_7_Normal = 0x09c,
Spill_0_Other = 0x0a0,
Spill_1_Other = 0x0a4,
Spill_2_Other = 0x0a8,
Spill_3_Other = 0x0ac,
Spill_4_Other = 0x0b0,
Spill_5_Other = 0x0b4,
Spill_6_Other = 0x0b8,
Spill_7_Other = 0x0bc,
Fill_0_Normal = 0x0c0,
Fill_1_Normal = 0x0c4,
Fill_2_Normal = 0x0c8,
Fill_3_Normal = 0x0cc,
Fill_4_Normal = 0x0d0,
Fill_5_Normal = 0x0d4,
Fill_6_Normal = 0x0d8,
Fill_7_Normal = 0x0dc,
Fill_0_Other = 0x0e0,
Fill_1_Other = 0x0e4,
Fill_2_Other = 0x0e8,
Fill_3_Other = 0x0ec,
Fill_4_Other = 0x0f0,
Fill_5_Other = 0x0f4,
Fill_6_Other = 0x0f8,
Fill_7_Other = 0x0fc,
Trap_Instruction = 0x100,
Last_Real_Exception = 0x200
} v9_exception_type_t;
typedef struct v9_memory_transaction {
generic_transaction_t s;
unsigned cache_virtual:1;
unsigned cache_physical:1;
unsigned side_effect:1;
unsigned priv:1;
unsigned red:1;
unsigned hpriv:1;
unsigned henb:1;
uint8 address_space;
uint8 prefetch_fcn;
sparc_access_type_t access_type;
/* if non-zero, the id needed to calculate the program counter */
intptr_t turbo_miss_id;
} v9_memory_transaction_t;
This is the Sparc specific memory transaction data structure. The generic data is stored in the s field.
The cache_virtual bit is set if this memory transaction corresponds to a TLB entry that has the CV (cache virtual) bit set. Conversely, the cache_physical bit corresponds to the TLB entry's CP (cache physical) bit and the side_effect bit corresponds to the E bit.
The priv bit is cleared if the memory transaction comes from one of the USER ASI's.
The red bit is set if the memory transaction was generated by a CPU which has the RED bit in the %pstate register set.
SPARC-V9 uses an address space identifier (ASI) to qualify memory access instructions. This is stored in the address_space field; it will be set to ASI_PRIMARY for "normal" memory transactions.
The prefetch_fcn field is only set for memory transactions of type Sim_Trans_Prefetch, for which it contains the fcn field of the prefetch instruction.
The access_type field describes the type of the access, as defined in the sparc_access_type_t enum. For example if a load is for a floating point register or a standard integer one.
typedef struct x86_memory_transaction {
generic_transaction_t s; /* Superclass */
processor_mode_t mode;
linear_address_t linear_address;
uint16 selector; /* Segment selector */
unsigned access_linear:1; /* Linear access */
unsigned io:1; /* I/O (port) access */
unsigned fault_as_if_write:1;
x86_access_type_t access_type;
x86_memory_type_t pat_type;
x86_memory_type_t mtrr_type;
x86_memory_type_t effective_type;
int sequence_number; /* used for -stall */
/* if non-zero, the id needed to calculate the program counter */
intptr_t turbo_miss_id;
} x86_memory_transaction_t;
typedef struct x86_memory_transaction p2_memory_transaction_t;
The s field contains generic information about memory operations (see generic_transaction_t).
The mode is the current mode (user or supervisor) of the cpu.
The linear_address contains the address for transactions with linear addresses.
The access_linear flag is set for all transactions with linear addresses.
The access_type field contains the type of the transaction.
typedef enum x86_access_type {
X86_Other, /* Access that is not categorized (rare) */
X86_Vanilla, /* "Normal" access, such as a MOV to/from
memory. X86_Vanilla operations use the STCs. */
X86_Instruction, /* Instruction fetch */
X86_Clflush, /* Cache line flush from CLFLUSH */
X86_Fpu_Env, /* Floating point environment (FLDENV, FNSTENV,
environment part of FRSTOR, FNSAVE) */
X86_Fpu_State, /* Register part of FRSTOR and FNSAVE */
X86_Idt, /* Interrupt descriptor table */
X86_Gdt, /* Global descriptor table */
X86_Ldt, /* Local descriptor table */
X86_Task_Segment, /* Task segment */
X86_Task_Switch, /* Task save/restore during a task switch */
X86_Far_Call_Parameter, /* Parameter copy in far call */
X86_Stack, /* Stack accesses during complex control flow
operations (exception handling, etc.) */
X86_Pml4, /* Page map level 4 table */
X86_Pdp, /* Page directory pointer table */
X86_Pd, /* Page directory table */
X86_Pt, /* Page table */
X86_Sse, /* 16-byte operations to/from SSE registers */
X86_Fpu, /* 10-byte and 16-byte operations to/from
X87 registers */
X86_Access_Simple, /* Device accesses (DMA) */
X86_Microcode_Update, /* Data read when performing a processor
microcode update */
X86_Non_Temporal, /* Non temporal store (example: MOVNTI) */
X86_Prefetch_3DNow, /* Prefetch with PREFETCH (3DNow!) */
X86_Prefetchw_3DNow, /* Prefetch with PREFETCHW (3DNow!) */
X86_Prefetch_T0, /* Prefetch with PREFETCHT0 (SSE) */
X86_Prefetch_T1, /* Prefetch with PREFETCHT1 (SSE) */
X86_Prefetch_T2, /* Prefetch with PREFETCHT2 (SSE) */
X86_Prefetch_NTA, /* Prefetch with PREFETCHNTA (SSE) */
X86_Loadall, /* State read by the loadall instruction */
X86_Atomic_Info, /* Transaction sent with size 0 to
finish an atomic transaction */
X86_Cmpxchg16b, /* CMPXCHG16B instruction */
X86_Smm_State /* SMM state structure */
} x86_access_type_t;
The effective memory type for the access is contained in
effective_type. The MMU calculates the effective memory type
using both the PAT type (in pat_type) and the MTRR type (in
mtrr_type).
typedef enum {
X86_None,
X86_Strong_Uncacheable, /* UC */
X86_Uncacheable, /* UC- */
X86_Write_Combining, /* WC */
X86_Write_Through, /* WT */
X86_Write_Back, /* WB */
X86_Write_Protected /* WP */
} x86_memory_type_t;
typedef enum {
X86_SFence = 1,
X86_LFence = 2,
X86_MFence = 3
} x86_sync_instruction_type_t;
| C/C++ | Python |
| attr_value_t, kind == Sim_Val_String | str (a Python string) |
| attr_value_t, kind == Sim_Val_Integer | int or long |
| attr_value_t, kind == Sim_Val_Floating | float |
| attr_value_t, kind == Sim_Val_List | list |
| attr_value_t, kind == Sim_Val_Data | tuple of integers (bytes) |
| attr_value_t, kind == Sim_Val_Nil | None |
| attr_value_t, kind == Sim_Val_Object | An object from the conf namespace. |
| attr_value_t, kind == Sim_Val_Dict | dict |
| attr_value_t, kind == Sim_Val_Boolean | bool |
| conf_class_t * | str (name of class) |
| conf_object_t * | An object from the conf namespace |