x86-486sx

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x86-486sx

Provided by: x86-486sx, x86-486sx-turbo
Class Hierarchy: conf-object → log-object → x86-486sx
Interfaces Implemented: log_object, x86, a20, interrupt_ack, exception, int_register, processor, event_poster
Description: The x86-486sx class implements an x86 processor.

Attributes

Attributes inherited from class conf-object

attributes, classname, component, iface, name, object_id, queue

Attributes inherited from class log-object

access_count, log_buffer, log_buffer_last, log_buffer_size, log_group_mask, log_groups, log_level, log_type_mask

Attribute List

a20mask: Optional attribute; read/write access; type: unknown type.
The a20mask.

access_type_name: Pseudo attribute; read-only access; ; integer indexed; indexed type: String.
Get string describing the specified access type (x86_access_type_t).

activity_state: Optional attribute; read/write access; type: unknown type.
Processor activity state.

address_width: Pseudo class attribute; read-only access; type: unknown type.
(phys-bits, virt-bits) Number of bits in physical and virtual addresses.

ah: Pseudo attribute; read/write access; type: unknown type.
Register ah (bits 8-15 from eax).

al: Pseudo attribute; read/write access; type: unknown type.
Register al (lower 8 bits of eax).

aprof_views

Session attribute; read/write access; type: [[o,i]*].

((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.

This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.

architecture: Pseudo class attribute; read-only access; type: unknown type.
Implemented architecture (x86)

ax: Pseudo attribute; read/write access; type: unknown type.
Register ax (lower 16 bits of eax).

bh: Pseudo attribute; read/write access; type: unknown type.
Register bh (bits 8-15 from ebx).

big_endian: Pseudo attribute; read-only access; type: b.
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.

bl: Pseudo attribute; read/write access; type: unknown type.
Register bl (lower 8 bits of ebx).

block_init: Optional attribute; read/write access; type: unknown type.
INIT will be blocked if this flag is set.

block_nmi: Optional attribute; read/write access; type: unknown type.
NMI will be blocked if this flag is set.

block_smi: Optional attribute; read/write access; type: unknown type.
SMI will be blocked if this flag is set.

bp: Pseudo attribute; read/write access; type: unknown type.
Register bp (lower 16 bits of ebp).

branch_prof_support: Pseudo attribute; read-only access; type: b.
True if this processor supports branch profiling in -stall mode, false otherwise.

bx: Pseudo attribute; read/write access; type: unknown type.
Register bx (lower 16 bits of ebx).

ch: Pseudo attribute; read/write access; type: unknown type.
Register ch (bits 8-15 from ecx).

cl: Pseudo attribute; read/write access; type: unknown type.
Register cl (lower 8 bits of ecx).

committed_instructions: Session attribute; read/write access; type: unknown type.
Number of committed instructions for an out of order target. Same as step count for an in-order Simics.

cpl: Optional attribute; read/write access; type: unknown type.
Current privilige level.

cpu_group: Optional attribute; read/write access; type: Object or Nil.
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface.

cpuid_2_eax: Optional attribute; read/write access; type: unknown type.
Value returned in EAX for CPUID when input EAX == 2.

cpuid_2_ebx: Optional attribute; read/write access; type: unknown type.
Value returned in EBX for CPUID when input EAX == 2.

cpuid_2_ecx: Optional attribute; read/write access; type: unknown type.
Value returned in ECX for CPUID when input EAX == 2.

cpuid_2_edx: Optional attribute; read/write access; type: unknown type.
Value returned in EDX for CPUID when input EAX == 2.

cpuid_brand_id: Optional attribute; read/write access; type: unknown type.
Brand ID for CPUID.

cpuid_clflush_size: Optional attribute; read/write access; type: unknown type.
Size of CLFLUSH as reported by CPUID.

cpuid_extended_family: Optional attribute; read/write access; type: unknown type.
Extended family for CPUID.

cpuid_extended_model: Optional attribute; read/write access; type: unknown type.
Extended model for CPUID.

cpuid_family: Optional attribute; read/write access; type: unknown type.
Family for CPUID.

cpuid_l2_cache_assoc: Optional attribute; read/write access; type: unknown type.
Level 2 cache information returned by CPUID function 8000.0006.

cpuid_l2_cache_line_size: Optional attribute; read/write access; type: unknown type.
Level 2 cache information returned by CPUID function 8000.0006.

cpuid_l2_cache_lines_per_tag: Optional attribute; read/write access; type: unknown type.
Level 2 cache information returned by CPUID function 8000.0006.

cpuid_l2_cache_size_kb: Optional attribute; read/write access; type: unknown type.
Level 2 cache information returned by CPUID function 8000.0006.

cpuid_logical_processor_count: Optional attribute; read/write access; type: unknown type.
Count of logical processors for CPUID. Setting this to non-zero will enable the HTT feature bit (bit 28).

cpuid_model: Optional attribute; read/write access; type: unknown type.
Model for CPUID.

cpuid_physical_apic_id: Optional attribute; read/write access; type: unknown type.
Physical local APIC ID for CPUID.

cpuid_processor_name: Optional attribute; read/write access; type: unknown type.
Processor name for CPUID.

cpuid_stepping: Optional attribute; read/write access; type: unknown type.
Stepping for CPUID.

cpuid_vendor_id: Optional attribute; read/write access; type: unknown type.
Vendor ID string for CPUID.

cr0: Optional attribute; read/write access; type: unknown type.
Control register 0.

cr2: Optional attribute; read/write access; type: unknown type.
Control register 2.

cr3: Optional attribute; read/write access; type: unknown type.
Control register 3.

cr4: Optional attribute; read/write access; type: unknown type.
Control register 4.

cs: Optional attribute; read/write access; type: unknown type.
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

current_context: Session attribute; read/write access; type: Object.
Current context object.

cx: Pseudo attribute; read/write access; type: unknown type.
Register cx (lower 16 bits of ecx).

cycle_fractions: Optional attribute; read/write access; type: Integer.
Modeling parameter related to processor scheduling.

cycles: Optional attribute; read/write access; type: Integer.
Time measured in cycles from machine start.

dbg_compile_block: Pseudo attribute; write-only access; type: unknown type.
Force compile of block.

dh: Pseudo attribute; read/write access; type: unknown type.
Register dh (bits 8-15 from edx).

di: Pseudo attribute; read/write access; type: unknown type.
Register di (lower 16 bits of edi).

disable_block_merge: Optional attribute; read/write access; type: unknown type.
Internal.

disabled_breakpoints_update_dr6: Optional attribute; read/write access; type: unknown type.
Set to non-zero if you want debug breakpoints that are not enabled either through DR7.L nor DR7.G to still set the B bits in DR6.

dl: Pseudo attribute; read/write access; type: unknown type.
Register dl (lower 8 bits of edx).

do_allocate_target_registers: Session class attribute; read/write access; type: unknown type.
Target register allocation enable.

do_reissue: Session attribute; write-only access; type: Integer.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.

dr0: Optional attribute; read/write access; type: unknown type.
Debug register 0.

dr1: Optional attribute; read/write access; type: unknown type.
Debug register 1.

dr2: Optional attribute; read/write access; type: unknown type.
Debug register 2.

dr3: Optional attribute; read/write access; type: unknown type.
Debug register 3.

dr6: Optional attribute; read/write access; type: unknown type.
Debug register 6.

dr7: Optional attribute; read/write access; type: unknown type.
Debug register 7.

ds: Optional attribute; read/write access; type: unknown type.
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

dx: Pseudo attribute; read/write access; type: unknown type.
Register dx (lower 16 bits of edx).

eax: Optional attribute; read/write access; type: unknown type.
General purpose register.

ebp: Optional attribute; read/write access; type: unknown type.
General purpose register.

ebx: Optional attribute; read/write access; type: unknown type.
General purpose register.

ecx: Optional attribute; read/write access; type: unknown type.
General purpose register.

edi: Optional attribute; read/write access; type: unknown type.
General purpose register.

edx: Optional attribute; read/write access; type: unknown type.
General purpose register.

eflags: Optional attribute; read/write access; type: unknown type.
Flag register.

eip: Optional attribute; read/write access; type: unknown type.
Instruction pointer.

enabled_flag: Optional attribute; read/write access; type: b.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.

es: Optional attribute; read/write access; type: unknown type.
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

esi: Optional attribute; read/write access; type: unknown type.
General purpose register.

esp: Optional attribute; read/write access; type: unknown type.
General purpose register.

event_desc: Pseudo attribute; read-only access; ; integer indexed; indexed type: [[o|n,s,i]*].
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).

exception_description: Pseudo attribute; read-only access; type: String.
Description of current exception. Only valid when read from the Core_Exception hap. The value can be Nil in which case the exception number, source, and optional error code can be used to gain an understanding of why the exception triggered.

exception_error_code: Pseudo attribute; read-only access; type: Integer.
Error code for the current exception. Only valid when read from the Core_Exception hap. This attribute is undefined for exceptions that do not have an error code.

ext: Optional attribute; read/write access; type: unknown type.
A bit indicating if the current exception is external.

ferr_status: Optional attribute; read/write access; type: unknown type.
Status for the ferr output pin.

ferr_target: Optional attribute; read/write access; type: unknown type.
Object to which the FERR pin (used for external x87 exception emulation) is connected.

fpu_commit_last_instr: Optional attribute; read/write access; type: unknown type.
If this attribute is non-zero, the next FPU instruction will shift the FPU instruction, operand, and opcode values.

fpu_control: Optional attribute; read/write access; type: unknown type.
X86 register.

fpu_last_instr_pointer0: Optional attribute; read/write access; type: unknown type.
FPU instruction pointer offset.

fpu_last_instr_pointer1: Optional attribute; read/write access; type: unknown type.
Next FPU instruction pointer offset.

fpu_last_instr_selector0: Optional attribute; read/write access; type: unknown type.
FPU instruction pointer selector.

fpu_last_instr_selector1: Optional attribute; read/write access; type: unknown type.
Next FPU instruction pointer selector.

fpu_last_opcode0: Optional attribute; read/write access; type: unknown type.
FPU instruction opcode.

fpu_last_opcode1: Optional attribute; read/write access; type: unknown type.
Next FPU instruction opcode.

fpu_last_operand_pointer0: Optional attribute; read/write access; type: unknown type.
FPU operand pointer offset.

fpu_last_operand_pointer1: Optional attribute; read/write access; type: unknown type.
Next FPU operand pointer offset.

fpu_last_operand_selector0: Optional attribute; read/write access; type: unknown type.
FPU operand pointer selector.

fpu_last_operand_selector1: Optional attribute; read/write access; type: unknown type.
Next FPU operand pointer selector.

fpu_regs: Optional attribute; read/write access; type: unknown type.
((empty, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9){8}). X86 floating point registers. The 8 80-bits registers is stored as a list of 11 bytes. The first byte tells if the register is empty (1) or not (0). The other bytes contain the register value with the lowest (least significant) bits in b0 and the highest (most significant bits in b9.

fpu_status: Optional attribute; read/write access; type: unknown type.
X86 register.

fpu_tag: Optional attribute; read/write access; type: unknown type.
X86 register.

freq_mhz: Required attribute; read/write access; type: i|f.
Processor clock frequency in MHz.

fs: Optional attribute; read/write access; type: unknown type.
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

gdtr_base: Optional attribute; read/write access; type: unknown type.
Global descriptor table base.

gdtr_limit: Optional attribute; read/write access; type: unknown type.
Global descriptor table limit.

gs: Optional attribute; read/write access; type: unknown type.
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

halt_steps: Optional attribute; read/write access; type: unknown type.
Number of steps waiting in HLT instructions.

idtr_base: Optional attribute; read/write access; type: unknown type.
Interrupt descriptor table base.

idtr_limit: Optional attribute; read/write access; type: unknown type.
Interrupt descriptor table limit.

ignne_status: Optional attribute; read/write access; type: unknown type.
Status for the ignne input pin.

in_smm: Optional attribute; read/write access; type: unknown type.
Set iff the processor is in system management mode.

instruction_fetch_line_size: Session attribute; read/write access; type: Integer.
Instruction fetch line size for this processor.

instruction_fetch_mode: Session attribute; read/write access; type: String.
Instruction fetch mode

ip: Pseudo attribute; read/write access; type: unknown type.
Register ip (lower 16 bits of eip).

is_stalling: Optional attribute; read/write access; type: b.
TRUE if the processor is currently stalling by request of a timing-model.

latch_init: Optional attribute; read/write access; type: unknown type.
INIT is currently latched.

latch_nmi: Optional attribute; read/write access; type: unknown type.
NMI is currently latched.

latch_smi: Optional attribute; read/write access; type: unknown type.
SMI is currently latched.

ldtr: Optional attribute; read/write access; type: unknown type.
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

load_test_file: Pseudo attribute; write-only access; type: String.
Internal. Load test file into memory.

lock_granularity: Optional attribute; read/write access; type: Integer.
Lock granularity of atomic instructions

lsq_enabled: Optional attribute; read/write access; type: Integer.
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"

mai_debug: Optional attribute; read/write access; type: String.
(internal) Set debug file for MAI

memory_profiling_granularity_log2: Pseudo attribute; read-only access; type: Integer.
Base 2 logarithm of memory profiling granularity.

min_cacheline_size: Pseudo attribute; read-only access; type: Integer.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).

mmu_stalling: Optional attribute; read/write access; type: Integer.
0: mmu stalling off when using MAI, 1: mmu stalling on when using MAI.

mode_counters: Pseudo attribute; read-only access; type: [[sii]*].
((name, user-value, supervisor-value), ...) List of per-mode counters.

ooo_mode: Optional attribute; read/write access; type: String.
"in-order" or "micro-architecture".

panic_string: Pseudo class attribute; read-only access; type: String.
Description of the last internal simulator panic.

pending_debug_exception: Optional attribute; read/write access; type: unknown type.
A debug exception is pending. Additional information about the exception is stored in pending_debug_exception_dr6.

pending_debug_exception_dr6: Optional attribute; read/write access; type: unknown type.
Valid if pending_debug_exception is non-zero. Attribute has the same format as the DR6 register.

pending_exception: Optional attribute; read/write access; type: unknown type.
If this attribute is non-zero, then we have a pending exception that will be handled before the next instruction. This will only happen for exceptions that are handled after instruction completion (traps).

pending_exception_error_code: Optional attribute; read/write access; type: unknown type.
Error code to be delivered on the next pending exception.

pending_exception_instruction_length: Optional attribute; read/write access; type: unknown type.
Length of pending trap instruction.

pending_interrupt: Optional attribute; read/write access; type: unknown type.
This attribute is non-zero when an interrupt should be taken before the next instruction.

pending_vector: Optional attribute; read/write access; type: unknown type.
Pending interrupt vector. Only valid between interrupt ack and the actual handling of the interrupt (when pending_vector_valid is set).

pending_vector_valid: Optional attribute; read/write access; type: unknown type.
Valid flag for pending_vector.

physical_bits: Pseudo class attribute; read-only access; type: Integer.
Number of physical address bits.

physical_io: Optional attribute; read/write access; type: Object.
I/O space. Must implement both the memory-space and the breakpoint interface.

physical_memory: Required attribute; read/write access; type: Object.
Physical memory space. Must implement both the memory-space and the breakpoint interface.

port_space: Required attribute; read/write access; type: unknown type.
I/O space of the cpu targeted by the IN, INS, OUT, and OUTS instructions. Must implement either the port interface (typically an instance of the port-space class), or the lookup interface (typically an instance of the memory-space class).

processor_number: Optional attribute; read/write access; type: Integer.
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.

reorder_buffer_size: Optional attribute; read/write access; type: unknown type.
Size of the reorder buffer (for x86 MAI).

si: Pseudo attribute; read/write access; type: unknown type.
Register si (lower 16 bits of esi).

sp: Pseudo attribute; read/write access; type: unknown type.
Register sp (lower 16 bits of esp).

ss: Optional attribute; read/write access; type: unknown type.
Segment register. All fields are stored in a list of integers as follows: (selector, b, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

stall_time: Optional attribute; read/write access; type: Integer.
The number of cycles the processor will stall

stalling_info: Optional attribute; read/write access; type: [iii].
If is_stalling is set, this contains information about the current memory operation.

step_per_cycle_mode: Optional attribute; read/write access; type: String.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.

step_queue: Optional attribute; read/write access; type: [[o|n,a,s,i]*].
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.

step_rate: Optional attribute; read/write access; type: [iii].
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.

steps: Optional attribute; read/write access; type: Integer.
Number steps executed since machine start.

temporary_interrupt_mask: Optional attribute; read/write access; type: unknown type.
If non-zero, interrupts are temporarily disabled even though EFLAGS.IF may be set.

time_queue: Optional attribute; read/write access; type: [[o|n,a,s,i]*].
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.

tlb: Required attribute; read/write access; type: Object.
Object handling the TLBs for this CPU.

tr: Optional attribute; read/write access; type: unknown type.
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid) The limit field always specifies the limit in bytes.

turbo_alloc_memory: Session class attribute; read/write access; type: unknown type.
Force allocation of memory.

turbo_block_info: Pseudo class attribute; read/write access; type: unknown type.
Block stats.

turbo_blocks: Pseudo class attribute; read-only access; type: [[iiiii]*].
Compiled blocks.

turbo_code_area: Session class attribute; read-only access; type: unknown type.
Code areas.

turbo_debug_level: Session class attribute; read/write access; type: unknown type.
Turbo engine debug level.

turbo_execution_mode: Session class attribute; read/write access; type: unknown type.
Turbo enable.

turbo_exhaust_current_block: Pseudo class attribute; write-only access; type: unknown type.
Allocate all code space in the current block.

turbo_global_vars: Pseudo class attribute; read-only access; type: unknown type.
Global symbols.

turbo_heap_start: Session class attribute; read-only access; type: unknown type.
Start of heap.

turbo_link_targets: Pseudo class attribute; read-only access; type: unknown type.
Link targets.

turbo_max_compiled_blocks: Session class attribute; read/write access; type: unknown type.
Max number of blocks.

turbo_max_trace_size: Session class attribute; read/write access; type: unknown type.
Max translation unit size.

turbo_processor_offsets: Pseudo class attribute; read-only access; type: unknown type.
Processor offsets.

turbo_register_offsets: Pseudo class attribute; read-only access; type: unknown type.
Register offsets.

turbo_segbase_optimization_delay: Session class attribute; read/write access; type: unknown type.
Segment base optimization delay.

turbo_stat: Pseudo class attribute; read/write access; type: unknown type; string indexed; indexed type: unknown type.
Stats.

turbo_stats: Pseudo class attribute; write-only access; type: unknown type.
When set to one, print stats.

turbo_threshold: Session class attribute; read/write access; type: unknown type.
Translation threshold.

turbo_use_direct_sp: Session class attribute; read/write access; type: unknown type.
Direct stack pointer enable.

turbo_use_dstc_direct_lookup: Session class attribute; read/write access; type: unknown type.
Direct DSTC lookup enable.

turbo_use_off_page_chaining: Session class attribute; read/write access; type: unknown type.
Off page chaining enable.

waiting_device: Optional attribute; read/write access; type: unknown type.
The device that requested the waiting interrupt. Only valid when waiting_interrupt is non-zero.

waiting_interrupt: Optional attribute; read/write access; type: unknown type.
If an interrupt is requested, but it cannot be immediately handled because interrupts are masked.

Command List

Commands defined by interface log_object: log, log-group, log-level, log-size, log-type
Commands defined by interface x86: memory-configuration, msrs, pregs-fpu, pregs-sse, print-gdt, print-idt
Commands defined by interface processor: add-memory-profiler, aprof-views, attach-branch-recorder, break-cr, cycle-break, cycle-break-absolute, detach-branch-recorder, disable, disassemble, down, enable, frame, info, instruction-fetch-mode, io-read, io-write, list, list-memory-profilers, load-binary, logical-to-physical, pos, pregs, pregs-hyper, print-statistics, print-time, psym, read, read-reg, register-number, remove-memory-profiler, set-context, set-pc, stack-trace, start-instruction-profiling, step-break, step-break-absolute, sum, symval, trace-cr, unbreak-cr, untrace-cr, up, wait-for-cycle, wait-for-step, write, write-reg, x

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