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ppc440gp-dma
- Provided by
-
440gp-devices
- Class Hierarchy
-
conf-object → log-object → ppc440gp-dma
- Interfaces Implemented
-
log_object, io_memory
- Ports
-
Reset (signal)
- Description
-
The ppc440gp-dma device implements the functionality of the ppc440gp direct memory access (DMA) device.
Attributes
- Attributes inherited from class conf-object
-
attributes, classname, component, iface, name, object_id, queue
- Attributes inherited from class log-object
-
access_count, log_buffer, log_buffer_last, log_buffer_size, log_group_mask, log_groups, log_level, log_type_mask
- Attribute List
-
- DMA0_CR0
- Optional attribute; read/write access; type: Integer.
Channel Control Register 0
- DMA0_CR1
- Optional attribute; read/write access; type: Integer.
Channel Control Register 1
- DMA0_CR2
- Optional attribute; read/write access; type: Integer.
Channel Control Register 2
- DMA0_CR3
- Optional attribute; read/write access; type: Integer.
Channel Control Register 3
- DMA0_CTC0
- Optional attribute; read/write access; type: Integer.
Count and Control Register 0
- DMA0_CTC1
- Optional attribute; read/write access; type: Integer.
Count and Control Register 1
- DMA0_CTC2
- Optional attribute; read/write access; type: Integer.
Count and Control Register 2
- DMA0_CTC3
- Optional attribute; read/write access; type: Integer.
Count and Control Register 3
- DMA0_DAH0
- Optional attribute; read/write access; type: Integer.
Destination Address High Register 0
- DMA0_DAH1
- Optional attribute; read/write access; type: Integer.
Destination Address High Register 1
- DMA0_DAH2
- Optional attribute; read/write access; type: Integer.
Destination Address High Register 2
- DMA0_DAH3
- Optional attribute; read/write access; type: Integer.
Destination Address High Register 3
- DMA0_DAL0
- Optional attribute; read/write access; type: Integer.
Destination Address Low Register 0
- DMA0_DAL1
- Optional attribute; read/write access; type: Integer.
Destination Address Low Register 1
- DMA0_DAL2
- Optional attribute; read/write access; type: Integer.
Destination Address Low Register 2
- DMA0_DAL3
- Optional attribute; read/write access; type: Integer.
Destination Address Low Register 3
- DMA0_POL
- Optional attribute; read/write access; type: Integer.
Polarity Configuration Register
- DMA0_SAH0
- Optional attribute; read/write access; type: Integer.
Source Address High Register 0
- DMA0_SAH1
- Optional attribute; read/write access; type: Integer.
Source Address High Register 1
- DMA0_SAH2
- Optional attribute; read/write access; type: Integer.
Source Address High Register 2
- DMA0_SAH3
- Optional attribute; read/write access; type: Integer.
Source Address High Register 3
- DMA0_SAL0
- Optional attribute; read/write access; type: Integer.
Source Address Low Register 0
- DMA0_SAL1
- Optional attribute; read/write access; type: Integer.
Source Address Low Register 1
- DMA0_SAL2
- Optional attribute; read/write access; type: Integer.
Source Address Low Register 2
- DMA0_SAL3
- Optional attribute; read/write access; type: Integer.
Source Address Low Register 3
- DMA0_SGC
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Command Register
- DMA0_SGH0
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address High Register 0
- DMA0_SGH1
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address High Register 1
- DMA0_SGH2
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address High Register 2
- DMA0_SGH3
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address High Register 3
- DMA0_SGL0
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address Low Register 0
- DMA0_SGL1
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address Low Register 1
- DMA0_SGL2
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address Low Register 2
- DMA0_SGL3
- Optional attribute; read/write access; type: Integer.
Scatter/Gather Descriptor Address Low Register 3
- DMA0_SLP
- Optional attribute; read/write access; type: Integer.
Sleep Mode Register
- DMA0_SR
- Optional attribute; read/write access; type: Integer.
Status Register
- cpu
- Required attribute; read/write access; type: Object.
CPU object (for reset callback).
- interrupt_device
- Required attribute; read/write access; type: Object.
Object to receive interrupts.
- irq_levels
- Optional attribute; read/write access; type: [iiii].
Interrupt numbers per channel. Default is [12,13,14,15].
- memory
- Required attribute; read/write access; type: Object.
Memory space object for packet transactions.
- pending_interrupts
- Optional attribute; read/write access; type: [iiii].
Interrupts that currently are pending (the exact representation is internal to this device model).
- transfer_cycles
- Optional attribute; read/write access; type: Integer.
Number of cycles for each DMA transfer. Default is 1000 cycles.
Command List
- Commands defined by interface log_object
-
log, log-group, log-level, log-size, log-type
- Commands
-
| status | print dynamic information about device |
Command Descriptions
-
<ppc440gp-dma>.status
- Synopsis
-
<ppc440gp-dma>.status
- Description
-
Print detailed dynamic information about the simulated device.
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