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ppc405gp-mal

Provided by
405gp-devices
Class Hierarchy
conf-objectlog-objectppc405gp-mal
Interfaces Implemented
log_object, io_memory
Ports
Reset (signal)
Description
The ppc405gp-mal device implements the functionality of the ppc405gp memory access layer (MAL).

Attributes

Attributes inherited from class conf-object
attributes, classname, component, iface, name, object_id, queue
Attributes inherited from class log-object
access_count, log_buffer, log_buffer_last, log_buffer_size, log_group_mask, log_groups, log_level, log_type_mask
Attribute List
MAL0_CFG
Optional attribute; read/write access; type: Integer.

Configuration register

MAL0_ESR
Optional attribute; read/write access; type: Integer.

Error status register

MAL0_IER
Optional attribute; read/write access; type: Integer.

Interrupt enable register

MAL0_RCBS0
Optional attribute; read/write access; type: Integer.

RX channel 0 buffer size registers

MAL0_RCBS1
Optional attribute; read/write access; type: Integer.

RX channel 1 buffer size registers

MAL0_RXBADDR
Optional attribute; read/write access; type: Integer.

RX descriptor base address register

MAL0_RXCARR
Optional attribute; read/write access; type: Integer.

RX channel active reset register

MAL0_RXCASR
Optional attribute; read/write access; type: Integer.

RX channel active set register

MAL0_RXCTP0R
Optional attribute; read/write access; type: Integer.

RX channel 0 table pointer register

MAL0_RXCTP1R
Optional attribute; read/write access; type: Integer.

RX channel 1 table pointer register

MAL0_RXDEIR
Optional attribute; read/write access; type: Integer.

RX descriptor error interrupt register

MAL0_RXEOBISR
Optional attribute; read/write access; type: Integer.

RX end of buffer interrupt status register

MAL0_RXTATTRR
Optional attribute; read/write access; type: Integer.

RX PLB attribute register

MAL0_TXBADDR
Optional attribute; read/write access; type: Integer.

TX descriptor base address register

MAL0_TXCARR
Optional attribute; read/write access; type: Integer.

TX channel active reset register

MAL0_TXCASR
Optional attribute; read/write access; type: Integer.

TX channel active set register

MAL0_TXCTP0R
Optional attribute; read/write access; type: Integer.

TX channel 0 table pointer register

MAL0_TXCTP1R
Optional attribute; read/write access; type: Integer.

TX channel 1 table pointer register

MAL0_TXDEIR
Optional attribute; read/write access; type: Integer.

TX descriptor error interrupt register

MAL0_TXEOBISR
Optional attribute; read/write access; type: Integer.

TX end of buffer interrupt status register

MAL0_TXTATTRR
Optional attribute; read/write access; type: Integer.

TX PLB attribute register

cpu
Required attribute; read/write access; type: Object.

CPU object (for reset callback).

eob_levels
Optional attribute; read/write access; type: [ii].

Interrupt levels to be passed to the TX and RX end-of-buffer interrupt target objects respectively.

eob_targets
Optional attribute; read/write access; type: [oo].

Objects to receive TX and RX end-of-buffer interrupts.

interrupt_levels
Pseudo attribute; read/write access; type: [ii].

Deprecated (for backward compatibility only).

interrupts
Pseudo attribute; read/write access; type: [oo].

Deprecated (for backward compatibility only).

irq_dev
Pseudo attribute; read/write access; type: Object.

Deprecated (for backward compatibility only).

memory
Required attribute; read/write access; type: Object.

Memory space object for packet transactions.

next_rx_descriptor
Optional attribute; read/write access; type: [i{1}].

The index of rx descriptors to be processed next (per channel).

next_tx_descriptor
Optional attribute; read/write access; type: [i{2}].

The index of tx descriptors to be processed next (per channel).

pending_interrupts
Optional attribute; read/write access; type: Integer.

Interrupts that currently are pending (the exact representation is internal to this device model).

Command List

Commands defined by interface log_object
log, log-group, log-level, log-size, log-type

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