ppc405gp

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ppc405gp

Provided by: ppc405gp, ppc405gp-turbo
Class Hierarchy: conf-object → log-object → ppc405gp
Interfaces Implemented: log_object, simple_interrupt, exception, int_register, ppc, processor, event_poster
Ports: SRESET (signal), HRESET (signal)
Description: ppc405gp processor simulation

Attributes

Attributes inherited from class conf-object

attributes, classname, component, iface, name, object_id, queue

Attributes inherited from class log-object

access_count, log_buffer, log_buffer_last, log_buffer_size, log_group_mask, log_groups, log_level, log_type_mask

Attribute List

address_width: Pseudo class attribute; read-only access; type: unknown type.
(phys-bits, virt-bits) Number of bits in physical and virtual addresses.

aprof_views

Session attribute; read/write access; type: [[o,i]*].

((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.

This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.

architecture: Pseudo class attribute; read-only access; type: unknown type.
Implemented architecture (ppc32)

available_timebase_modes: Pseudo class attribute; read-only access; type: [s*].
Lists all available timebase modes (except the default 'null' mode)

big_endian: Pseudo attribute; read-only access; type: b.
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.

branch_prof_support: Pseudo attribute; read-only access; type: b.
True if this processor supports branch profiling in -stall mode, false otherwise.

ccr0: Optional attribute; read/write access; type: Integer.
Core Configuration register 0

chip_reset_target: Optional attribute; read/write access; type: n|o|[os].
Object listening to the chip reset signal. The object should implement the signal interface.

core_reset_target: Optional attribute; read/write access; type: n|o|[os].
Object listening to the core reset signal. The object should implement the signal interface.

cpu_group: Optional attribute; read/write access; type: Object or Nil.
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface and the ppc-broadcast-businterface.

cr: Optional attribute; read/write access; type: Integer.
Condition register

ctr: Optional attribute; read/write access; type: Integer.
Counter register

current_context: Session attribute; read/write access; type: Object.
Current context object.

cycle_fractions: Optional attribute; read/write access; type: Integer.
Modeling parameter related to processor scheduling.

cycles: Optional attribute; read/write access; type: Integer.
Time measured in cycles from machine start.

dac1: Optional attribute; read/write access; type: Integer.
Data Address Compare 1

dac2: Optional attribute; read/write access; type: Integer.
Data Address Compare 2

dbcr0: Optional attribute; read/write access; type: Integer.
Debug Control register 0

dbcr1: Optional attribute; read/write access; type: Integer.
Debug Control register 1

dbg_compile_block: Pseudo attribute; write-only access; type: unknown type.
Force compile of block.

dbsr: Optional attribute; read/write access; type: Integer.
Debug Status register

dcache: Optional attribute; read/write access; type: Object or Nil.
Cache object affected by data cache control instructions.

dccr: Optional attribute; read/write access; type: Integer.
Data Cache Cacheability

dcr_space: Required attribute; read/write access; type: Object.
Device control register space mappings

dcwr: Optional attribute; read/write access; type: Integer.
Data Cache Write-through

dear: Optional attribute; read/write access; type: Integer.
Data exception address

disable_watchdog_reboots: Optional attribute; read/write access; type: Integer.
(temporary) Disable reboot feature when watchdog triggers

do_allocate_target_registers: Session class attribute; read/write access; type: unknown type.
Target register allocation enable.

do_reissue: Session attribute; write-only access; type: Integer.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.

dvc1: Optional attribute; read/write access; type: Integer.
Data Value Compare 1

dvc2: Optional attribute; read/write access; type: Integer.
Data Value Compare 2

enabled_flag: Optional attribute; read/write access; type: b.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.

esr: Optional attribute; read/write access; type: Integer.
Exception syndrome Register

event_desc: Pseudo attribute; read-only access; ; integer indexed; indexed type: [[o|n,s,i]*].
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).

evpr: Optional attribute; read/write access; type: Integer.
Exception vector prefix reg

freq_mhz: Required attribute; read/write access; type: i|f.
Processor clock frequency in MHz.

gprs: Optional attribute; read/write access; type: [i{32}]; integer indexed; indexed type: Integer.
(r0, r1, ..., r31) General purpose registers

halt_steps: Optional attribute; read/write access; type: Integer.
Number of steps spent waiting in nap/doze mode.

iac1: Optional attribute; read/write access; type: Integer.
Instruction Address Compare 1

iac2: Optional attribute; read/write access; type: Integer.
Instruction Address Compare 2

iac3: Optional attribute; read/write access; type: Integer.
Instruction Address Compare 3

iac4: Optional attribute; read/write access; type: Integer.
Instruction Address Compare 4

icache: Optional attribute; read/write access; type: Object or Nil.
Cache object affected by instruction cache control instructions.

iccr: Optional attribute; read/write access; type: Integer.
Instruction Cache Cacheability

icdbr: Optional attribute; read/write access; type: Integer.
Instruction Cache Debug Data reg

in_sleep_state: Optional attribute; read/write access; type: Integer.
Non-zero if CPU is in nap/doze mode.

instruction_fetch_line_size: Session attribute; read/write access; type: Integer.
Instruction fetch line size for this processor.

instruction_fetch_mode: Session attribute; read/write access; type: String.
Instruction fetch mode

is_stalling: Optional attribute; read/write access; type: b.
TRUE if the processor is currently stalling by request of a timing-model.

lock_granularity: Optional attribute; read/write access; type: Integer.
Lock granularity of atomic instructions

lr: Optional attribute; read/write access; type: Integer.
Link register

lsq_enabled: Optional attribute; read/write access; type: Integer.
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"

mai_debug: Optional attribute; read/write access; type: String.
(internal) Set debug file for MAI

memory_profiling_granularity_log2: Pseudo attribute; read-only access; type: Integer.
Base 2 logarithm of memory profiling granularity.

min_cacheline_size: Pseudo attribute; read-only access; type: Integer.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).

mmu_real_region: Optional attribute; read/write access; type: [i,i].
(address, mask) Specifies a region for identity address translation.

mode_counters: Pseudo attribute; read-only access; type: [[sii]*].
((name, user-value, supervisor-value), ...) List of per-mode counters.

msr: Optional attribute; read/write access; type: Integer.
Machine state register

msr_bit_names: Pseudo attribute; read-only access; type: [s*].
(bit0name, bit1name... bit32/64name) of the names for each MSR bit defined on this PowerPC processor. Bits not defined are names with an empty string

ooo_mode: Optional attribute; read/write access; type: String.
"in-order" or "micro-architecture".

pc: Optional attribute; read/write access; type: Integer.
Program counter

pending_exceptions: Optional attribute; read/write access; type: [s*].
List of pending exceptions

pending_irq_name: Pseudo attribute; read-only access; type: String.
Name of an interrupt just about to be taken handled

physical_memory: Required attribute; read/write access; type: Object.
Physical memory space. Must implement both the memory-space and the breakpoint interface.

pid: Optional attribute; read/write access; type: Integer.
Process ID

pit: Optional attribute; read/write access; type: Integer.
Programmable Interval Timer

pit_reload_value: Optional attribute; read/write access; type: Integer.
PIT auto-reload value. (Last value written via mtspr to PIT)

processor_number: Optional attribute; read/write access; type: Integer.
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.

pvr: Optional attribute; read/write access; type: Integer.
Processor version

reservation_address: Optional attribute; read/write access; type: Integer.
Atomic reservation address

reservation_size: Pseudo attribute; read-only access; type: Integer.
Atomic reservation block size

reserve: Optional attribute; read/write access; type: Integer.
Atomic reservation

sgr: Optional attribute; read/write access; type: Integer.
Storage Guarded Register

sler: Optional attribute; read/write access; type: Integer.
Storage Little-endian Register

spr_list: Pseudo attribute; read-only access; type: [[issiiiiiiiiii]*].
List of defined SPRs.

sprg0: Optional attribute; read/write access; type: Integer.
Provided for OS use

sprg1: Optional attribute; read/write access; type: Integer.
Provided for OS use

sprg2: Optional attribute; read/write access; type: Integer.
Provided for OS use

sprg3: Optional attribute; read/write access; type: Integer.
Provided for OS use

sprg4: Optional attribute; read/write access; type: Integer.
Provided for OS use

sprg5: Optional attribute; read/write access; type: Integer.
Provided for OS use

sprg6: Optional attribute; read/write access; type: Integer.
Provided for OS use

sprg7: Optional attribute; read/write access; type: Integer.
Provided for OS use

srr0: Optional attribute; read/write access; type: Integer.
Machine save/restore register 0

srr1: Optional attribute; read/write access; type: Integer.
Machine save/restore register 1

srr2: Optional attribute; read/write access; type: Integer.
Machine save/restore register 2

srr3: Optional attribute; read/write access; type: Integer.
Machine save/restore register 3

stall_time: Optional attribute; read/write access; type: Integer.
The number of cycles the processor will stall

stalling_info: Optional attribute; read/write access; type: [iii].
If is_stalling is set, this contains information about the current memory operation.

stc_cache_w: Optional attribute; read/write access; type: b.
If set, memory mapped with W=1 will be cached in the STC, making access faster but slowing access for instructions which would trap when W=1. This is for improving simulator performance and should have no other effect.

step_per_cycle_mode: Optional attribute; read/write access; type: String.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.

step_queue: Optional attribute; read/write access; type: [[o|n,a,s,i]*].
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.

step_rate: Optional attribute; read/write access; type: [iii].
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.

steps: Optional attribute; read/write access; type: Integer.
Number steps executed since machine start.

su0r: Optional attribute; read/write access; type: Integer.
Storage User defined 0 Register

system_reset_target: Optional attribute; read/write access; type: n|o|[os].
Object listening to the system reset signal. The object should implement the signal interface.

tbl: Optional attribute; read/write access; type: Integer.
Timebase lower register

tbu: Optional attribute; read/write access; type: Integer.
Timebase upper register

tcr: Optional attribute; read/write access; type: Integer.
Timer Control register

temperature: Optional attribute; read/write access; type: Integer.
Temperature of the processor (C)

time_queue: Optional attribute; read/write access; type: [[o|n,a,s,i]*].
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.

timebase_freq_mhz: Required attribute; read/write access; type: i|f.
Frequency (in MHz) for time base update

timebase_mode

Optional attribute; read/write access; type: s|n.

By default, the timebase is connected to the simulated cycles of a processor. Since Simics schedules processors (including hardware threads) in a round-robin fashion, where each processor gets to execute a large amount of instructions, this can cause problems. One example would be when one processor writes the value of timebase to memory at the end of it's quantum, and another processors compares this to the timebase at the beginning of the quantum; time will appear to have moved backwards. Therefore, there are additional timebase modes available that tries to work around these problems. Note that these modes may cause timing irregularies, depending on what software is running on the simulated machine.

The available modes are:

stall - a processor will be stalled til the end of it's quantum whenever it reads the timebase.

quantum-locked - timebase will only change on quantum boundaries.

fast-forward - timebase is fast forwarded when needed and then stopped until time (simulated cycles) has caught up with it.

Unless you know what you are doing, make sure the timebase mode on all processors (of the same class) are the same.

timebase_remainder: Optional attribute; read/write access; type: Integer.
Timebase remainder

timers_at_quantum_start: Optional attribute; read/write access; type: [[si]*].
Values of timer registers at quantum start. Used by quantum-locked timebase mode.

timers_enabled: Pseudo attribute; read/write access; type: Integer.
If 0, time base/decrementer stand still (internal use only)

tsr: Optional attribute; read/write access; type: Integer.
Timer Status register

turbo_alloc_memory: Session class attribute; read/write access; type: unknown type.
Force allocation of memory.

turbo_block_info: Pseudo class attribute; read/write access; type: unknown type.
Block stats.

turbo_blocks: Pseudo class attribute; read-only access; type: [[iiiii]*].
Compiled blocks.

turbo_code_area: Session class attribute; read-only access; type: unknown type.
Code areas.

turbo_debug_level: Session class attribute; read/write access; type: unknown type.
Turbo engine debug level.

turbo_execution_mode: Session class attribute; read/write access; type: unknown type.
Turbo enable.

turbo_exhaust_current_block: Pseudo class attribute; write-only access; type: unknown type.
Allocate all code space in the current block.

turbo_global_vars: Pseudo class attribute; read-only access; type: unknown type.
Global symbols.

turbo_heap_start: Session class attribute; read-only access; type: unknown type.
Start of heap.

turbo_link_targets: Pseudo class attribute; read-only access; type: unknown type.
Link targets.

turbo_max_compiled_blocks: Session class attribute; read/write access; type: unknown type.
Max number of blocks.

turbo_max_trace_size: Session class attribute; read/write access; type: unknown type.
Max translation unit size.

turbo_processor_offsets: Pseudo class attribute; read-only access; type: unknown type.
Processor offsets.

turbo_register_offsets: Pseudo class attribute; read-only access; type: unknown type.
Register offsets.

turbo_stat: Pseudo class attribute; read/write access; type: unknown type; string indexed; indexed type: unknown type.
Stats.

turbo_stats: Pseudo class attribute; write-only access; type: unknown type.
When set to one, print stats.

turbo_threshold: Session class attribute; read/write access; type: unknown type.
Translation threshold.

turbo_use_direct_sp: Session class attribute; read/write access; type: unknown type.
Direct stack pointer enable.

turbo_use_dstc_direct_lookup: Session class attribute; read/write access; type: unknown type.
Direct DSTC lookup enable.

turbo_use_off_page_chaining: Session class attribute; read/write access; type: unknown type.
Off page chaining enable.

usprg0: Optional attribute; read/write access; type: Integer.
User general register 0

utlb: Optional attribute; read/write access; type: [[i,i]*].
(((tlbhi0, tlblo0),(tlbhi1, tlblo1)).....) Unified TLB

watchdog_target: Optional attribute; read/write access; type: n|o|[os].
Object listening to the watchdog signal. The object should implement the signal interface.

xer: Optional attribute; read/write access; type: Integer.
Fixed-point exception register

zpr: Optional attribute; read/write access; type: Integer.
Zone Protection register

Command List

Commands defined by interface log_object

log, log-group, log-level, log-size, log-type

Commands defined by interface processor

add-memory-profiler, aprof-views, attach-branch-recorder, break-cr, cycle-break, cycle-break-absolute, detach-branch-recorder, disable, disassemble, down, enable, frame, info, instruction-fetch-mode, io-read, io-write, list, list-memory-profilers, load-binary, logical-to-physical, pos, pregs, pregs-hyper, print-statistics, print-time, psym, read, read-reg, register-number, remove-memory-profiler, set-context, set-pc, stack-trace, start-instruction-profiling, step-break, step-break-absolute, sum, symval, trace-cr, unbreak-cr, untrace-cr, up, wait-for-cycle, wait-for-step, write, write-reg, x

Commands

print-utlb	print unified tlb contents
temperature	set or query the temperature of the processor

Command Descriptions

<ppc405gp>.print-utlb
Synopsis: <ppc405gp>.print-utlb
Description: Prints the contents of the unified TLB of the processor.

<ppc405gp>.temperature
Synopsis: <ppc405gp>.temperature [degrees-celsius]
Description: If the simulated PowerPC processor is equipped with a TAU (Thermal Assist Unit), this command allows TAU related features to be tested. Without any arguments, the command prints the current set temperature. The temperature can be changed by specifying the wanted temperature. This command accesses the temperature attribute on the processor.

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