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i82443bx_agp

Provided by
82443BX
Class Hierarchy
conf-objectlog-objecti82443bx_agp
Interfaces Implemented
log_object, bridge, pci_bridge, io_memory, pci_device
Description
The i82443bx_agp class models the PCI to AGP bridge in the 82443BX Host Bridge/Controller.

Attributes

Attributes inherited from class conf-object
attributes, classname, component, iface, name, object_id, queue
Attributes inherited from class log-object
access_count, log_buffer, log_buffer_last, log_buffer_size, log_group_mask, log_groups, log_level, log_type_mask
Attribute List
config_register_info
Pseudo attribute; read-only access; type: [[isii]*].

Register info for all registered configuration registers. The format for each entry is (offset, name, size, write-mask).

config_registers
Optional attribute; read/write access; type: [i{64}]; integer indexed; indexed type: Integer.

The 64 PCI configuration registers, each 32 bits in size.

expansion_rom
Optional attribute; read/write access; type: [oii].

ROM object, map size, and map function number for the Expansion ROM.

interrupt_pin
Optional attribute; read/write access; type: [iiii].

State of the interrupt pin.

mapping_setup
Optional attribute; read/write access; type: [i{15}].

Attributes for mappings

mappings
Optional attribute; read/write access; type: [[i{5:8}]|[iiiiiiiio|nii]*].

List of all current PCI IO and memory mappings.

pci_bus
Optional attribute; read/write access; type: Object or Nil.

The PCI bus this device is connected to, implementing the pci-bus interface.

secondary_bus
Required attribute; read/write access; type: Object.

Secondary (downstream) PCI bus.

write_masks
Optional attribute; read/write access; type: [[ii]*].

Write masks for all registered configuration registers. The format for each entry is (offset, mask).

Command List

Commands defined by interface log_object
log, log-group, log-level, log-size, log-type
Commands
pci-headerprint PCI device header

Command Descriptions

<i82443bx_agp>.pci-header
Synopsis
<i82443bx_agp>.pci-header
Description
Print the PCI header, i.e the configuration registers.

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