i21554-prim

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Provided by: i21554
Class Hierarchy: conf-object → log-object → i21554-prim
Interfaces Implemented: log_object, io_memory, pci_device, bridge
Description: The i21554-prim models the primary interface on the PCI to PCI bridge

Attributes inherited from class conf-object

attributes, classname, component, iface, name, object_id, queue

Attributes inherited from class log-object

access_count, log_buffer, log_buffer_last, log_buffer_size, log_group_mask, log_groups, log_level, log_type_mask

Attribute List

base_setup: Optional attribute; read/write access; type: unknown type.
The setup register values. The i21554 device can be programmed by an on board serial prom that will initialize the setup registers. In Simics this is done by setting this attribute. The seven registers are in the following order: downstream memory 0, downstream I/O / memory 1, downstream memory 2, downstream memory 3 (lower), downstream memory 3 (upper), upstream I/O / memory 0 and upstream memory 1.

base_translate: Optional attribute; read/write access; type: unknown type.
Translation bases.

bridge_mappings: Optional attribute; read/write access; type: unknown type.
List of all current PCI I/O and memory mappings.

chip_control0: Optional attribute; read/write access; type: unknown type.
Chip Control 0 register.

config_register_info: Pseudo attribute; read-only access; type: [[isii]*].
Register info for all registered configuration registers. The format for each entry is (offset, name, size, write-mask).

config_registers: Optional attribute; read/write access; type: [i{64}]; integer indexed; indexed type: Integer.
The 64 PCI configuration registers, each 32 bits in size.

down_conf_addr: Optional attribute; read/write access; type: unknown type.
Downstream configuration address register.

expansion_rom: Optional attribute; read/write access; type: [oii].
ROM object, map size, and map function number for the Expansion ROM.

interrupt_pin: Optional attribute; read/write access; type: [iiii].
State of the interrupt pin.

mappings: Optional attribute; read/write access; type: [[i{5:8}]|[iiiiiiiio|nii]*].
List of all current PCI IO and memory mappings.

pci_bus: Optional attribute; read/write access; type: Object or Nil.
The PCI bus this device is connected to, implementing the pci-bus interface.

scnd_interface: Required attribute; read/write access; type: unknown type.
Secondary interface object for the bridge

write_masks: Optional attribute; read/write access; type: [[ii]*].
Write masks for all registered configuration registers. The format for each entry is (offset, mask).

Commands defined by interface log_object: log, log-group, log-level, log-size, log-type

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