-- testbed for the SR latch

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behav of tb is
  signal S,R,Q,Q_b : std_logic;
begin  
  test: process
  begin
    S <= '0';
    R <= '0';
    wait for 50 ns;
    -- activate set
    S <= '1';
    wait for 10 ns;
    S <= '0';
    wait for 50 ns;
    -- activate reset
    R <= '1';
    wait for 10 ns;
    R <= '0';
    wait for 50 ns;
    -- activate both: bad.
    R <= '1';
    S <= '1';
    wait for 10 ns;
  end process;

  -- hook up the d_latch as the unit under test (UUT)
  UUT: entity work.sr_latch
    port map (
      s   => S,
      r   => R,
      q   => Q,
      q_b => Q_b);
end behav;