-- testbed for reg

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behav of tb is
  signal c,l : std_logic;
  signal Q,D : std_logic_vector(2 downto 0);
begin  
  clock: process
  begin
    c <= '0', '1' after 20 ns; -- set c to '0' immediately and then to
                               -- '1' 20 ns later 
    wait for 40 ns;
  end process;

  data: process
  begin
    l <= '0';
    D <= "011";                 -- set the three bits in D
    wait for 100 ns;
    l <= '1';
    wait for 40 ns;
    l <= '0';
    D(0) <= '1';                -- seet the three bits another way
    D(1) <= '1';
    D(2) <= '0';
    wait for 100 ns;
  end process;

  
  -- hook up the reg as the unit under test (UUT)
  UUT: entity work.reg
    generic map (
      n => 3)
    port map (
      clock => c,
      load  => l,
      Q     => Q,
      D     => D);
end behav;