-- testbed for the PET D flip-flop

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behav of tb is
  signal D,C,Q,Q_b : std_logic;
begin  
  clock: process
      -- the control will be a regular clock pulse
  begin
    C <= '0';
    wait for 50 ns;
    C <= '1';
    wait for 50 ns;
  end process;

  signals: process
      -- change the data to see what happens
  begin
    D <= '1';
    wait for 55 ns;
    D <= '0';
    wait for 30 ns;
  end process;

  -- hook up a pet_d as the unit under test (UUT)
  UUT: entity work.pet_d
    port map (
      c   => C,
      d   => D,
      q   => Q,
      q_b => Q_b);
end behav;