-- testbed for the D latch

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behav of tb is
  signal D,C,Q,Q_b : std_logic;
begin  
  test: process
  begin
    D <= '0';
    C <= '0';
    wait for 50 ns;
    C <= '1';
    wait for 20 ns;
    C <= '0';
    wait for 50 ns;
    C <= '1';
    D <= '1';
    wait for 20 ns;
  end process;

  -- hook up the d_latch as the unit under test (UUT)
  UUT: entity work.d_latch
    port map (
      c   => C,
      d   => D,
      q   => Q,
      q_b => Q_b);
end behav;