-- testbed for count

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behav of tb is
  signal clock,load,count,carry : std_logic;
  signal Q,D : std_logic_vector(3 downto 0);
begin  
  clock_process: process
  begin
    clock <= '0', '1' after 20 ns; -- set c to '0' immediately and then to
                                   -- '1' 20 ns later 
    wait for 40 ns;
  end process;

  data_process: process
  begin
    load <= '0';
    count <= '0';
    -- first, try to load it.
    D <= "1101";
    wait for 115 ns;
    load <= '1';
    wait for 40 ns;
    load <= '0';
    D <= "0000";
    wait for 100 ns;
    -- now do some incrementing
    count <= '1';
    wait for 80 ns;
    count <= '0';
    wait for 40 ns;
    count <= '1';
    wait for 40 ns;
    count <= '0';
  end process;

  
  -- hook up the count as the unit under test (UUT)
  UUT: entity work.count
    port map (
      clock => clock,
      count => count,
      load  => load,
      carry => carry,
      Q     => Q,
      D     => D);
end behav;