-- VHDL for a syncronous counter with parallel load

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
  -- the ..._unsigned library lets us do arithmetic on binary-coded numbers
  -- ie. add one to the register.

entity count is
  port (
    D           : in  std_logic_vector(3 downto 0);
    Q           : out std_logic_vector(3 downto 0);
    count, load : in  std_logic;
    clock       : in  std_logic;
    carry       : out std_logic := '0');
end count;

architecture behav of count is
  -- you can't read from an output port, which we need to do to increment,
  -- so, duplicate it in internal signals:
  signal Q_int : std_logic_vector(0 to 3);
  signal here : std_logic := '0';       -- added for testing
begin
  count_process: process (clock)
    -- we don't update Q here, just Q_int.  Updating Q is in the next process.
  begin
    if rising_edge(clock) and load='1' then
      Q_int <= D;
      carry <= '0';

    elsif rising_edge(clock) and count='1' then
      -- Activates "here", so we can check in the simulator when we enter this
      -- part of the process.  Only used for debugging, but left for
      -- illustration:
      here <= '1', '0' after 5 ns;

      -- properly set the carry bit:
      if Q_int = "1111" then
        carry <= '1';
      else
        carry <= '0';
      end if;
      
      -- increment the counter:
      Q_int <= Q_int + "0001";
    end if;
  end process;

  -- Update Q whenever Q_int changes:
  Q_update: process (Q_int)
  begin
    Q <= Q_int after 3 ns;
  end process Q_update;

end behav;