-- testbed for the full adder

library ieee;
use ieee.std_logic_1164.all;

-- the testbed has no external connections
entity tb is
end tb;

architecture behav of tb is
  signal X,Y,Z,S,C : std_logic;
begin  
  -- the test process will just periodically fiddle with the input signals,
  -- so we can see what comes out.
  test: process
  begin
    X <= '0';
    Y <= '0';
    Z <= '0';
    wait for 100 ns;
    X <= '1';
    wait for 50 ns;
    Y <= '1';
    wait for 50 ns;
    Z <= '1';
    wait for 50 ns;
  end process;

  -- hook up the full_adder as the unit under test (UUT)
  UUT: entity work.full_adder(struct)
    port map (
      X => X,
      Y => Y,
      Z => Z,
      S => S,
      C => C);
end behav;