-- A description of the half-adder

library ieee;
use ieee.std_logic_1164.all;

-- the input/output signals
entity half_adder is  
  port (
    x, y : in  std_logic;
    s, c : out std_logic);
end half_adder;

-- a structural description of it:
architecture struct of half_adder is
  
begin
  -- XOR1 is an instance of the xor_gate, using the behavioural definition.
  XOR1: entity work.xor_gate(behav)
    port map (
      a => x,
      b => y,
      c => s);

  -- AND1 is an instance of the and_gate, using the behavioural definition.  
  AND1: entity work.and_gate(behav)
    port map (
      a => x,
      b => y,
      c => c);

end struct;