-- definitions of some basic gates

-- the and_gate
library ieee;
use ieee.std_logic_1164.all;

-- the inputs will be called a,b and the output is c.
entity and_gate is
  port (
    a, b : in  std_logic;
    c    : out std_logic);
end and_gate;

-- give a behavioural description of the gate:
architecture behav of and_gate is
begin
  and_process: process(a, b)
  begin
    c <= a and b after 2 ns;            -- set the output signal after
                                        -- a 2ns delay
  end process;

end behav;



-- the or_gate
library ieee;
use ieee.std_logic_1164.all;

entity or_gate is
  port (
    a, b : in  std_logic;
    c    : out std_logic);
end or_gate;

architecture behav of or_gate is
begin
  or_process: process(a, b)
  begin
    c <= a or b after 2 ns;
  end process;

end behav;





-- the xor gate

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
  port (
    a, b : in  std_logic;
    c    : out std_logic);
end xor_gate;

architecture behav of xor_gate is
begin
  xor_process: process(a, b)
  begin
    c <= a xor b after 2 ns;
  end process;

end behav;