-- A description of the full-adder

library ieee;
use ieee.std_logic_1164.all;


-- the input/output signals
entity full_adder is  
  port (
    X, Y, Z : in  std_logic;
    S, C : out std_logic);
end full_adder;

-- a behavioural description of it:
architecture behav of full_adder is
  begin
    FA: process(X,Y,Z)
      variable tmp : std_logic;
      begin
        tmp := X xor Y;
        S <= tmp xor Z after 3 ns;
        C <= (x and y) or (z and tmp) after 5 ns;
      end process;
  end behav;  










  


-- a structural description of it:
architecture struct of full_adder is
  signal T1,T2,T3 : std_logic;          -- we need some internal signals
  
begin
  -- HA1 is an instance of the half_adder, using the structural definition.
  HA1: entity work.half_adder(struct)
    port map (
      x  => X,
      y  => Y,
      s  => T1,
      c  => T3);
  
  -- HA2 is an instance of the half_adder, using the structural definition.
  HA2: entity work.half_adder(struct)
    port map (
      x => T1,
      y => Z,
      s => S,
      c => T2);

  -- OR1 is an instance of the or_gate, using the behavioural definition.
  OR1: entity work.or_gate(behav)
    port map (
      a => T2,
      b => T3,
      c => C);
    
end struct;