CMPT 250 Assignment 3

Due November 12, 2002.

For this assignment, you can use the IEEE std_logic libraries. There is a brief reference to the std_logic libraries on the course web site. There are several functions in them that will change some parts of this assignment from horrible coding exercises to one line, so you should have a look.

It would probably be a good idea to create a directory for this assignment; in fact, it might be easier to create one directory per entity so you have separate Makefile and sim.scr files for each.

You must use the given file names, entity names and port descriptions. There are two reasons: (i) If you don't, things might not fit together when we want to combine the parts in assignment 4; and (ii) it will make marking them much easier, letting us do some automated testing of your models.

On this assignment, and the remaining assignments, there will be marks allocated for the style of your code. You should just make sure you use appropriate variable/signal names, comment hard-to-understand parts, etc.

Multiplexer

In a file named mux.vhd create a behavioural description of a 2-to-1 multiplexer. You should use this entity declaration:

entity mux is
  generic (
    n : integer);  -- number of bits per word
  port (
    A, B : in  std_logic_vector(n-1 downto 0);
    S    : in  std_logic;
    Y    : out std_logic_vector(n-1 downto 0));
end mux;

When S is 0, the A output should be selected; when S is 1, the B output should be selected. All output should have a propogation delay of 1 ns.

Logic Unit

In a file named logic.vhd create a behavioural description of the "logic circuit" used in the ALU, as seen on pp. 363-364. You should use this entity declaration:

entity logic is
  generic (
    n : integer);  -- number of bits per word
  port (
    A,B    : in  std_logic_vector(n-1 downto 0);
    S0, S1 : in  std_logic;
    G      : out std_logic_vector(n-1 downto 0));
end logic;

All output should have a propogation delay of 1 ns.

The std_logic libraries define functions to do logical operations on every part of a vector signal. You cannot use those for this part. [You'll have to use loops.]

B Input Logic

In a file named binput.vhd create a behavioural description of the "B input logic" used in the arithmetic circuit, as seen on pp. 361-363. You should use this entity declaration:

entity binput is
  generic (
    n : integer);  -- number of bits per word
  port (
    B      : in  std_logic_vector(n-1 downto 0);
    S0, S1 : in  std_logic;
    Y      : out std_logic_vector(n-1 downto 0));
end binput;

All output should have a propogation delay of 2 ns.

Shifter

In a file named shifter.vhd create a behavioural description of an n-bit barrel shifter. You should use this entity declaration:

entity shifter is
  generic (
    n : integer;   -- number of bits per word
    k : integer);  -- number of bits in positions specifier
  port (
    D : in  std_logic_vector(n-1 downto 0);
    S : in  std_logic_vector(k-1 downto 0);
    Y : out std_logic_vector(n-1 downto 0));
end shifter;

This circuit should rotate the bits of the input, D, to the left by S positions. The S holds a k-bit unsigned integer value. Typically, we'll create this circuit with 2^k = n, but not necessarily.

All output should have a propogation delay of 2 ns.

Submitting

You have to use the Submission server to submit your work. You should submit the files mux.vhd, logic.vhd, binput.vhd and shifter.vhd.

You can do this by typing these commands (change into your assignment directory if you haven't already):

tar cvf a3.tar  mux.vhd logic.vhd binput.vhd shifter.vhd
gzip a3.tar

Then, submit the file a3.tar.gz. If you want to submit a ZIP file instead, you can do that but figuring out how is your problem.

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