Due Oct 18, 2002.
The next three assignments will (hopefully) fit together into a final "project" where you will use the parts from assignments 2 and 3 to create a large system in assignment 4. If it works properly, the three assignments should have roughly equal difficulty.
The focus will be more on behavioural descriptions than the first assignment. You will have to use more of the VHDL language. You will need to reference either the Student's Guide to VHDL (recommended text) or the VHDL Cookbook.
For this assignment, you can use the IEEE std_logic libraries.
There is a brief reference to the std_logic libraries on the course web site. There are several functions in them that will change some parts of this assignment from horrible coding exercises to one line, so you should have a look.
It would probably be a good idea to create a directory for this assignment; in fact, it might be easier to create one directory per entity so you have separate Makefile and sim.scr files for each.
You must use the given file names, entity names and port descriptions. There are two reasons: (i) If you don't, things might not fit together when we want to combine the parts in assignment 4; and (ii) it will make marking them much easier, letting us do some automated testing of your models.
On this assignment, and the remaining assignments, there will be marks allocated for the style of your code. You should just make sure you use appropriate variable/signal names, comment hard-to-understand parts, etc.
In a file named id.vhd create a behavioural description of the instruction decoder for the CPU. The circuit is described in Section 8.9, starting on p. 431. You should use this entity declaration:
entity id is
port (
opcode : in std_logic_vector(6 downto 0);
DR, SA, SB : in std_logic_vector(2 downto 0);
DA, AA, BA, BC : out std_logic_vector(2 downto 0);
MB, MD, RW, MW, PL, JB : out std_logic;
FS : out std_logic_vector(4 downto 0));
end id;Note that your description must be behavioural, not structural, even though there is a structure diagram on p. 432. The point is for you to think a little about how the circuit works, not just translating a picture to VHDL.
All output should have a propogation delay of 2 ns.
There is some less-than-clear notation in the circuit diagram for the Instruction Decoder in the text. Here's what it means: [PDF of vector AND]
The branch control circuit for the processor is introduced in section 8.9. It isn't well described there; hopefully the description here will fill in the gaps. The meanings of the input ports are as follows:
In a file bc.vhd, you should implement the branch control using a behavioural description for this entity:
entity bc is
port (
C, N, V, Z, PL, JB : in std_logic;
BC : in std_logic_vector(2 downto 0);
INC, JUMP : out std_logic);
end bc;
If we aren't branching, the branch control should send a 1 on the INC port and 0 on the JUMP port. This will connect to the program counter and indicate that it should increment. If we are branching or jumping, it should send a 1 for the JUMP port and 0 for INC. This will indicate that the program counter should add its data input to its current value.
If we are doing a conditional branch (PL=1 and JB=0), then the circuit should check the value of the status bit indicated by BC. If the status bit is 1, it should do the branch (send JUMP=1), otherwise the PC should increment (send INC=1).
For an unconditional branch (PL=1 and JB=1), we should send 1 to JUMP, regardless of the values in the status bits.
All output should have a propogation delay of 3 ns.
The final piece you'll be creating from the control unit is the program counter. In a file pc.vhd, create a behavioural description of this register.
entity pc is
generic (
n : integer); -- number of bits in the stored value.
port (
clock : in std_logic;
data_in : in std_logic_vector(n-1 downto 0);
add, inc : in std_logic;
data_out : out std_logic_vector(n-1 downto 0));
end pc;
All actions of the PC should be triggered by the rising edge of the clock signal. When the add signal is 1, the value from data_in should be added to the stored value. When inc is 1, the stored value should be incremented. If both are 1, the behaviour is undefined. The generic value n indicates the number of bits stored in the register.
The value in the program counter should be initialized to 0 at the beginning of the simulation. All output should have a propogation delay of 2 ns.
You have to use the Submission server to submit your work. You should submit the files id.vhd, bc.vhd and pc.vhd.
You can do this by typing these commands (change into your assignment directory if you haven't already):
tar cvf a2.tar id.vhd bc.vhd pc.vhd gzip a2.tar
Then, submit the file a2.tar.gz. If you want to submit a ZIP file instead, you can do that but figuring out how is your problem.
Return to CMPT 250 Assignments.
Copyright Greg Baker, last modified October 2002.