Due Sept 27, 2002.
mux4.vhd
, create a behavioural description of a 4 x 1 multiplexer, with this entity declaration:
entity mux4 is port ( s0, s1, d0, d1, d2, d3 : in std_logic; y : out std_logic); end mux4;
The output should have a propagation delay of 4 ns for any input change.
A full (one bit) adder can be created using two multiplexers as follows: [PDF of full adder]
In a file full_adder.vhd
, create a structural VHDL description of a full adder with this entity declaration:
entity full_adder is port ( X, Y, Z : in std_logic; S, C : out std_logic); end adder;
You can use the negater provided in the neg.vhd
file. Note that this entity should have identical behaviour to the full adder from lecture (except for different propagation delays).
For this part, you will create a structural description of a 4-bit ripple-carry adder, using the full adder from the previous part. The circuit looks like this: [PDF of ripple-carry adder]
You will have to use vector signals for input and output in this circuit; the individual components of the vectors will be connected to the full adders. Use this entity and name the file adder4.vhd
:
entity adder4 is port ( X, Y : in std_logic_vector(3 downto 0); S : out std_logic_vector(3 downto 0); C_in : in std_logic; C_out : out std_logic); end adder4;
If you don't have the full adder from the previous part working, you can use the full adder from lecture for testing (don't hand that in, of course). Just copy those files into the same directory and vhdlan
those instead of your model.
You have to use the Submission server to submit your work. You should submit the files mux4.vhd
, full_adder.vhd
and adder4.vhd
.
You can do this by typing these commands (change into your assignment directory if you haven't already):
tar cvf a1.tar mux4.vhd full_adder.vhd adder4.vhd gzip a1.tar
Then, submit the file a1.tar.gz
. If you want to submit a ZIP file instead, you can do that but figuring out how is your problem.
Return to CMPT 250 Assignments.
Copyright Greg Baker, last modified September 2002.