CMPT 250 Assignment 2

Due February 18, 2004.

In this assignment, we will continue to build parts of the example single-cycle architecture from the textbook.

On all assignments, there will be marks allocated for the style of your code. You should just make sure you use appropriate variable/signal names, comment hard-to-understand parts, etc.

Program Counter

In a file pc.vhd, create a behavioural description of this register,

entity pc is
  generic (
    n : integer);  -- number of bits in the stored value.
  port (
    clock    : in  std_logic;
    data_in  : in  std_logic_vector(n-1 downto 0);
    add, inc : in  std_logic;
    data_out : out std_logic_vector(n-1 downto 0));
end pc;

All actions of the PC should be triggered by the rising edge of the clock signal. When the add signal is 1, the value from data_in should be added to the stored value. When inc is 1, the stored value should be incremented. If both are 1, the behaviour is undefined. The generic value n indicates the number of bits stored in the register.

The value in the program counter should be initialized to 0 at the beginning of the simulation. All output should have a propogation delay of 2 ns.

Branch Control

The branch control circuit for the processor is introduced in section 8.9. It isn't well described there; hopefully the description here will fill in the gaps. The meanings of the input ports are as follows:

C, N, V, Z

Status bits from the datapath.

PL

We're doing a jump/branch if this is 1. Otherwise, just increment the PC.

JB

Are we doing a conditional jump or not? 0=conditional branch, 1=unconditional jump.

BC(1:0)

Controls the flag that is used for the conditional: 0=C, 1=N, 2=V, 3=Z. (also described on p. 431)

BC(2)

Use the negation of the flag indicated by BC(1:0) if this is 1.

In a file bc.vhd, you should implement the branch control using a behavioural description for this entity:

entity bc is
  port (
    C, N, V, Z, PL, JB : in  std_logic;
    BC                 : in  std_logic_vector(2 downto 0);
    INC, JUMP          : out std_logic);
end bc;

If we aren't branching, the branch control should send a 1 on the INC port and 0 on the JUMP port. This will connect to the program counter and indicate that it should increment. If we are branching or jumping, it should send a 1 for the JUMP port and 0 for INC. This will indicate that the program counter should add its data input to its current value.

If we are doing a conditional branch (PL=1 and JB=0), then the circuit should check the value of the status bit indicated by BC. If the status bit is 1, it should do the branch (send JUMP=1), otherwise the PC should increment (send INC=1).

For an unconditional branch (PL=1 and JB=1), we should send 1 to JUMP, regardless of the values in the status bits.

All outputs should have a propogation delay of 3 ns.

Logic Unit

In a file named logic.vhd create a behavioural description of the "logic circuit" used in the ALU, as seen on pp. 363-364. Use this entity declaration:

entity logic is
  generic (
    n : integer);  -- number of bits per word
  port (
    A,B    : in  std_logic_vector(n-1 downto 0);
    S0, S1 : in  std_logic;
    G      : out std_logic_vector(n-1 downto 0));
end logic;

All output should have a propogation delay of 1 ns.

The std_logic libraries define functions to do logical operations on every part of a vector signal. You must use those for this part. That is, you must use the and function that operates on two std_logic_vector signals.

B Input Logic

In a file named binput.vhd create a behavioural description of the "B input logic" used in the arithmetic circuit, as seen on pp. 361-363. You should use this entity declaration:

entity binput is
  generic (
    n : integer);  -- number of bits per word
  port (
    B      : in  std_logic_vector(n-1 downto 0);
    S0, S1 : in  std_logic;
    Y      : out std_logic_vector(n-1 downto 0));
end binput;

All output should have a propogation delay of 2 ns.

You cannot use the vector logic operations for this part. You'll have to use loops. [It's possible to implement this using vector operations, the restriction applies to this part only; the point is to make sure you know how to use VHDL looping constructs.]

Zero Fill and Sign Extender

These circuits are used to turn vector signals (with 3 or 6 bits) into wider signals (with 16 bits), representing the same value. The zero fill does this for unsigned values and the sign extend does the same for signed values.

In a file named extend.vhd, create behavioural architectures for these entities with no propogation delay (both should be in one file):

entity zf is
  generic (
    m : integer;
    n : integer);
  port (
    input  : in  std_logic_vector(m-1 downto 0);
    output : out std_logic_vector(n-1 downto 0));
end zf;

entity se is
  generic (
    m : integer;
    n : integer);
  port (
    input  : in  std_logic_vector(m-1 downto 0);
    output : out std_logic_vector(n-1 downto 0));
end se;

The output from the zero fill should be same unsigned integer as the input; the output from the sign extend should be the same signed integer. Here are some examples with m=3 and n=6:

Submitting

You have to use the Submission server to submit your work. You should submit the files pc.vhd, bc.vhd, logic.vhd, binput.vhd, extend.vhd.

You can do this by typing these commands (change into your assignment directory if you haven't already):

tar cvf a2.tar  pc.vhd bc.vhd logic.vhd binput.vhd extend.vhd
gzip a2.tar

Then, submit the file a2.tar.gz. If you want to submit a ZIP file instead, you can do that but figuring out how is your problem.