CMPT 250 Assignment 1

Due February 4, 2004.

Simple Multiplexer

In a file named smux.vhd create a behavioural description of a one-bit 2-to-1 multiplexer. You should use this entity declaration:

entity smux is
  port (
    A, B : in  std_logic;
    S    : in  std_logic;
    Y    : out std_logic);
end smux;

When S is 0, the A input should be selected; when S is 1, the B input should be selected. All output should have a propogation delay of 1 ns.

The behavour of the circuit when S is anything but '0' or '1' (eg. 'X' or 'U') is undefined. [Note: When a circuit has "undefined" behaviour means that anything can happen in that case. Don't ask what should happen if S is 'X'—the answer will be "I don't care; it doesn't matter."]

Testing the multiplexer

Create a testbench for the smux entity created above. The entity should be named tb_smux and in a file tb_smux.vhd. The testbench should test the multiplexer enough to convince you (and the marker) that it is working correctly.

You should also create a sim.scr file to go with this testbench. It should trace all necessary signals when the simulator starts. You should write the traces so it will work from the vhdlsim command. That is, they should be like trace /tb_smux/a, not just trace a (which can be used with the interactive debugger, vhdldbx).

You will need to create testbenches for all of the other entities you create for this course as well, but you won't generally have to submit them.

Vector Multiplexer

In a file named mux.vhd create a behavioural description of a 2-to-1 multiplexer. You should use this entity declaration:

entity mux is
  generic (
    n : integer);  -- number of bits per word
  port (
    A, B : in  std_logic_vector(n-1 downto 0);
    S    : in  std_logic;
    Y    : out std_logic_vector(n-1 downto 0));
end mux;

When S is 0, the A input should be selected; when S is 1, the B input should be selected. All output should have a propogation delay of 1 ns.

JK flip-flop

In a file named jk.vhd, create a behavioural description of a postitive-edge triggered JK flip-flop.

entity jk is
  port (
    c, j, k : in  std_logic;
    q, q_b  : out std_logic);
end jk;

The output should only change on the rising edge of the control (c) signal. The behaviour for the various values of j and k are summarized in the text in the table on p. 194. The q and q_b outputs should have a propogation delay of 2 ns.

Instruction Decoder

In a file named id.vhd create a behavioural description of the instruction decoder for the CPU. The circuit is described in Section 8.9, starting on p. 431. You should use this entity declaration:

entity id is
  port (
    opcode                 : in  std_logic_vector(6 downto 0);
    DR, SA, SB             : in  std_logic_vector(2 downto 0);
    DA, AA, BA, BC         : out std_logic_vector(2 downto 0);
    MB, MD, RW, MW, PL, JB : out std_logic;
    FS                     : out std_logic_vector(4 downto 0));
end id;

Note that your description must be behavioural, not structural, even though there is a structure diagram on p. 432. The point is for you to think a little about how the circuit works, not just translating a picture to VHDL.

All output should have a propogation delay of 2 ns.

There is some less-than-clear notation in the circuit diagram for the Instruction Decoder in the text. Here's what it means: [PDF of vector AND]

Submitting

You have to use the Submission server to submit your work. You should submit the files smux.vhd, tb_smux.vhd, sim.scr, mux.vhd, jk.vhd, id.vhd.

You can do this by typing these commands (change into your assignment directory if you haven't already):

tar cvf a1.tar  smux.vhd tb_smux.vhd sim.scr mux.vhd jk.vhd id.vhd
gzip a1.tar

Then, submit the file a1.tar.gz. If you want to submit a ZIP file instead, you can do that but figuring out how is your problem.