library ieee;
use ieee.std_logic_1164.all;
entity passthrough is
  generic (
    n : integer
  );
  port (
    i : in  std_logic_vector(n-1 downto 0);
    o : out std_logic_vector(n-1 downto 0)
  );
end passthrough;
architecture behav of passthrough is
begin
  o <= i;
end behav;



library ieee;
use ieee.std_logic_1164.all;
entity rotate is
end rotate;

architecture struct of rotate is
  signal input, output : std_logic_vector(3 downto 0);
  signal temp : std_logic_vector(3 downto 0);
begin
  temp <= input(2 downto 0) & input(3);
  
  PT: entity work.passthrough
    generic map (
      n => 4
    )
    port map (
      i => temp,
      o => output
    );
  
  driver: process
  begin
    input <= "1100";
    wait for 100 ns;
  end process;
end struct;