library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity adder is
  generic (
    n : integer);
  port (
    A, B : in std_logic_vector(n-1 downto 0);
    output : out std_logic_vector (n-1 downto 0));
end adder;

architecture behav of adder is
begin
  add_process: process (A, B)
  begin
    output <= conv_std_logic_vector ( conv_integer(A) + conv_integer(B), n );
  end process;
end behav;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mul10 is
  generic (
    n : integer := 8);
  port (
    input : in std_logic_vector(n-1 downto 0);
    output : out std_logic_vector(n-1 downto 0));
end mul10;

architecture struct of mul10 is
  signal mul2, mul8 : std_logic_vector(n-1 downto 0);
begin
  mul2 <= input(n-2 downto 0) & "0";
  mul8 <= input(n-4 downto 0) & "000";
 
  ADD: entity work.adder
    generic map ( n=>n )
    port map (
      A => mul2,
      B => mul8,
      output => output);
  
end struct;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb is
end tb;

architecture behav of tb is
  signal input,output : std_logic_vector(7 downto 0);
begin
  DRIVE: process
  begin
    input <= conv_std_logic_vector(5,8);
    wait for 100 ns;
    input <= conv_std_logic_vector(7,8);
    wait for 100 ns;
    input <= conv_std_logic_vector(13,8);
    wait for 100 ns;
  end process;
  
  UUT: entity work.mul10
    generic map (n=>8)
    port map (
      input => input,
      output => output);
end behav;