Due by 12:00 noon on Wednesday, June 6, in the CMPT-150-ARC drop boxes outside K9507. Make sure you put your assignment in the box labeled for CMPT-150-ARC.

Question 1.(2 marks) Answer problem 2-8(b) from the text.

 Original expression: F=ABC+~A~C+~A~B
to convert to AND and complement, we use demorgan to convert OR operations (X+Y+Z) to AND ( ~(~X~Y~Z) ):
F=~(~(ABC)~(~A~C)~(~A~B)

Question 2.(6 marks) Answer problem 2-14(a) and (c) from the text.

(a)

F=XY+~XZ

(c)

F=~A~B+~C

Question 3.(8 marks) Answer problem 2-16(b) and (c) from the text.

(b)

F=WX+~XZ

(c)

F=~AB+~B~D+BD

Question 4.(8 marks) Answer problem 2-32(b) from the text.

Question 5.(16 marks) A parity generator is a circuit which will prepare a word of bits to be sent and received using parity error correction. The circuit takes a word of data as input, and produces a parity bit as output. The word of data and the parity bit are transmitted together.
A parity decoder is a circuit which receives a parity-encoded transmission, and uses the parity bit to check the transmitted word for errors.

(a) Design a parity generator and a parity decoder for 4-bit words. The parity generator should use odd parity, which means that the value of the parity bit will ensure that the 5-bit word-plus-parity-bit transmission always contains an odd number of '1's. The parity decoder should then produce a '0' (meaning no error) if the 5-bit word-plus-parity-bit transmission contains an odd number of '1's, and should produce a '1' (meaning error) if the transmission contains an even number of '1's.

(b) Show your design procedure and justify any design decisions. Implement your circuits in DesignWorks, and test both circuits. Jusitfy the test cases you use. Make sure you test the parity decoder for cases where there was an error in transmission, as well as in cases where there was more than one error in transmission.

(c) Discuss some advantages and disadvantages of this type of parity as an error correction scheme.

SOLUTION

Parity Generator:
The parity generator has 4 inputs and 1 output. We want the combined 5 bits to have an odd number of 1s. This means that if the 4-bit input word has an even number of 1s, the parity bit should be 1, and if the 4-bit input word has an odd number of 1a, the parity bit should be 0. This implies that the parity bit is the even function. We know that XOR is the odd function, so XNOR is the even function. a 4-bit XNOR will provide the functionality we need.

Parity Decoder:
The parity decoder has 5 inputs and 1 output. The output will tell us if the transmission was valid or not. We must decide how to interpret the output. I will decide that output=1 indicates a successful transmission (odd number of 1s) and output=0 indicates a non-successful transmission (Even number of 1s). The circuit therefore should be a 5-bit XOR (which is the odd function). DesignWorks does not have a 5-bit XOR, so we take a 4-bit XOR and a 2 bit XOR and combine them to create a 5-bit XOR. We can do this because in class we learned that

The circuits:

And the timing diagrams:

The first 5 lines of the timing diagram show the exhaustive test for the parity generator. We can see that there are always an odd number of "1"s between those 5 signals. In particular, at A there is one "1". The input word was "0000" and the parity bit provided the "1" to bring the count to one. At B, the input word was "1101" which already has an odd number of "1"s, so the parity bit was set to "0".

The last 6 lines of the timing diagram show the exhaustive test for the parity decoder. The following test cases are noted:

1. All inputs 0. The 4-bit word was "0000", so the parity bit should have been "1" but it was not. The circuit classifies the transmission as invalid.
2. Input word was "0110", parity bit was correctly set to "1" so the transmission is valid.
3. Input word was "1011", parity bit was correctly set to "0" so the transmission is valid
4. Input word was "1011", but parity suggests that there should have been an even number of "1"s in the word. Transmission is invalid.