Assignment 2 CMPT-150-ARC

CMPT-150 Assignment 2

Available Wednesday, May 23, 2001

Due Wednesday, June 6, 2001

Due by 12:00 noon on Wednesday, June 6, in the CMPT-150-ARC drop boxes outside K9507. Make sure you put your assignment in the box labeled for CMPT-150-ARC.

Question 1. Answer problem 2-8(b) from the text.

Question 2. Answer problem 2-14(a) and (c) from the text.

Question 3. Answer problem 2-16(b) and (c) from the text.

Question 4. Answer problem 2-32(b) from the text.

Question 5. A parity generator is a circuit which will prepare a word of bits to be sent and received using parity error correction. The circuit takes a word of data as input, and produces a parity bit as output. The word of data and the parity bit are transmitted together.
A parity decoder is a circuit which receives a parity-encoded transmission, and uses the parity bit to check the transmitted word for errors.

(a) Design a parity generator and a parity decoder for 4-bit words. The parity generator should use odd parity, which means that the value of the parity bit will ensure that the 5-bit word-plus-parity-bit transmission always contains an odd number of '1's. The parity decoder should then produce a '0' (meaning no error) if the 5-bit word-plus-parity-bit transmission contains an odd number of '1's, and should produce a '1' (meaning error) if the transmission contains an even number of '1's.

(b) Show your design procedure and justify any design decisions. Implement your circuits in DesignWorks, and test both circuits. Jusitfy the test cases you use. Make sure you test the parity decoder for cases where there was an error in transmission, as well as in cases where there was more than one error in transmission.