library ieee;
use ieee.std_logic_1164.all;

entity sr_latch is
  port (
    s, r   : in  std_logic;
    q, q_b : out std_logic);
end sr_latch;

architecture behav of sr_latch is
begin
  sr_process: process (s, r)
  begin
    if s='1' and r='1' then
      -- the SR latch has this undefined state.
      q <= 'X';
      q_b <= 'X';
    elsif s = '1' then
      -- set
      q <= '1';
      q_b <= '0';
    elsif r = '1' then
      -- reset
      q <= '0';
      q_b <= '1';
    end if;
  end process sr_process;
end behav;